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Pull requests: llvm/circt

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Pull requests list

[RTG][Elaborator] Elaborate external ops with regions RTG Involving the `rtg` dialect
#10811 opened Jul 10, 2026 by youngar Member Loading…
1
[Arcilator] Add --jit-object-file option to dump JIT-compiled object Arc Involving the `arc` dialect
#10810 opened Jul 9, 2026 by fabianschuiki Contributor Loading…
2
[Moore] SimplifyRefs: lower concat_ref destinations of delayed assignments
#10808 opened Jul 9, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Fold case equality against x/z-bearing constants to its static verdict
#10807 opened Jul 9, 2026 by AmurG Contributor Loading…
1
[FIRRTL] Allow arbitrary LowerMemory dedup
#10805 opened Jul 9, 2026 by seldridge Member Loading…
1
[ImportVerilog] Support dynamic foreach loops
#10804 opened Jul 9, 2026 by AlviseDeFaveri Loading…
5
[FIRRTL] Add RWProbe force/release synthesis to ProbesToSignals
#10803 opened Jul 9, 2026 by prithayan Contributor Loading…
1
[ArcRuntime][InsertRuntime] Improve handling of trace file paths Arc Involving the `arc` dialect
#10802 opened Jul 9, 2026 by fzi-hielscher Contributor Loading…
1
[ImportVerilog] Look through labels on module-level concurrent assertions
#10796 opened Jul 8, 2026 by AmurG Contributor Loading…
1
[Sim][Moore] Make zero-operand queue.concat round-trippable
#10795 opened Jul 8, 2026 by AmurG Contributor Loading…
1
[LLHD] Add llhd.resample: pin event-trigger samples to their check block
#10794 opened Jul 8, 2026 by AmurG Contributor Loading…
4
[LLHD] Deseq: handle signals with multiple drivers soundly
#10793 opened Jul 8, 2026 by AmurG Contributor Loading…
1
[ExportVerilog] Legalize EnumFieldAttr types in anonymous enum pass
#10791 opened Jul 8, 2026 by ConvolutedDog Loading…
1
[Calyx] Avoid invalid intermediate IR in common-tail canonicalization
#10790 opened Jul 8, 2026 by skku970412 Loading…
1
[ImportVerilog][Moore][MooreToCore] Add $readmemb/$readmemh support ImportVerilog Moore
#10789 opened Jul 8, 2026 by VecoMr Member Loading…
3
[VerifToSMT] Keep assumptions asserted across BMC timesteps
#10788 opened Jul 7, 2026 by leizaf Contributor • Draft
1
[Arcilator] Support sim.proc.print with stream
#10778 opened Jul 6, 2026 by nanjo712 Contributor Loading…
5
[circt-bmc] handle 'verif.formal' / 'verif.contract' op in module
#10772 opened Jul 5, 2026 by Clo91eaf Contributor Loading…
15
[FIRRTL] Add --disable-line-wrap flag to emitter
#10765 opened Jul 3, 2026 by TaoBi22 Contributor Loading…
7
[FIRRTL][InferDomains] Add option to skip checking specific domains
#10763 opened Jul 2, 2026 by uenoku Member • Draft
1
Bump LLVM
#10756 opened Jul 2, 2026 by uenoku Member • Draft
2
[FSM] Eliminate mutually exclusive transition guards (#3577)
#10754 opened Jul 1, 2026 by arefinaa Loading…
2 tasks done
1
[circt-bmc] Add dbg.trace for BMC counterexample value tracking
#10747 opened Jul 1, 2026 by 5iri Contributor Loading…
6
[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions
#10746 opened Jun 30, 2026 by jpkirs Loading…
3
[Python] Fix ModuleLike.is_external for ops with no region
#10745 opened Jun 30, 2026 by uenoku Member Loading…
1
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