[LLHD] Deseq: handle signals with multiple drivers soundly

[AmurG]

llhd-deseq promotes a fed conditional drive to a seq.firreg plus an unconditional continuous drive even when the analyzed process is not the signal's only driver. A signal written by several processes takes the last write per write event, so the register drive clobbers every other process's write on the next delta. The common casualty is the bench idiom

initial begin read = 1; ... end          // one-shot t=0 init
always @(posedge clk) read <= ...;       // edge updates

where the initial block's value is silently lost: the register holds its power-on zero until the first clock edge.

Reproducer on current main (circt-opt --llhd-deseq)

hw.module @InitClobbered(in %clock: i1, in %d: i42) {
  %c0_i42 = hw.constant 0 : i42
  %c1_i42 = hw.constant 1 : i42
  %0 = llhd.constant_time <0ns, 1d, 0e>
  %1, %2 = llhd.process -> i42, i1 {          // always @(posedge clock)
    %true = hw.constant true
    %false = hw.constant false
    cf.br ^bb1(%c0_i42, %false : i42, i1)
  ^bb1(%3: i42, %4: i1):
    llhd.wait yield (%3, %4 : i42, i1), (%clock : i1), ^bb2(%clock : i1)
  ^bb2(%5: i1):
    %6 = comb.xor bin %5, %true : i1
    %7 = comb.and bin %6, %clock : i1
    cf.cond_br %7, ^bb1(%d, %true : i42, i1), ^bb1(%c0_i42, %false : i42, i1)
  }
  %3 = llhd.sig %c0_i42 : i42
  llhd.process {                              // initial begin sig = 1; end
    llhd.drv %3, %c1_i42 after %0 : i42
    llhd.halt
  }
  llhd.drv %3, %1 after %0 if %2 : i42
}

Output on current main: the init process survives, but the promoted register has no preset and its unconditional drive clobbers the init on the next delta.

llhd.process {
  llhd.drv %1, %c1_i42 after %0 : i42
  llhd.halt
}
%3 = seq.firreg %d clock %2 : i42
llhd.drv %1, %3 after %4 : i42

The fix classifies extra drivers instead of promoting blindly. A drive that provably executes exactly once at t=0 with a constant value (unconditional, zero delay, in the entry block of another process, no predecessors, cannot re-execute) folds into the promoted register's preset, which reproduces the constant from t=0 onward. Any other extra driver (non-constant, conditional, delayed, repeated, module-level continuous, or in llhd.final) keeps the process form.

Folding rather than always bailing matters: in mixed form, promoted registers on the same clock commit at clock evaluation before kept processes resume, so a kept process observes post-edge values of same-clock registers, a one-delta lead that breaks lockstep pipelines. We measured exactly that regression on two SVA local-variable benches under the bare guard, before adding the preset fold.

Tested: deseq.mlir gains @MultiDrivenInitFoldsToPreset, @MultiDrivenSignalKeepsProcess, and @MultiDrivenDelayedInitKeepsProcess.

Written with AI assistance; I've reviewed the diff and tests.

[circt-bot]

Results of circt-tests run for f12929b compared to results for 01b5614: no change to test results.