[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions#10746
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jpkirs wants to merge 6 commits into
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[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions#10746jpkirs wants to merge 6 commits into
jpkirs wants to merge 6 commits into
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fabianschuiki
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Jun 30, 2026
fabianschuiki
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This is really cool, thanks a lot for tackling these @jpkirs. Just a small nit about an accidental deletion in the code -- will probably break CI.
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| static LogicalResult | ||
| emitScanAssignments(Context &context, const Context::ScanStringResult &result, | ||
| Location loc) { | ||
| auto &builder = context.builder; | ||
| auto newBlockAfter = [&](Block *after) -> Block * { | ||
| auto block = std::make_unique<Block>(); | ||
| block->insertAfter(after); | ||
| return block.release(); | ||
| }; | ||
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| for (auto [destExpr, value, matched] : result.assignments) { | ||
| auto lhs = context.convertLvalueExpression(*destExpr); | ||
| if (!lhs) | ||
| return failure(); | ||
| auto cond = moore::ToBuiltinIntOp::create(builder, loc, matched); | ||
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| auto *assignBlock = newBlockAfter(builder.getInsertionBlock()); | ||
| auto *continuedBlock = newBlockAfter(assignBlock); | ||
| mlir::cf::CondBranchOp::create(builder, loc, cond, assignBlock, | ||
| continuedBlock); | ||
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| builder.setInsertionPointToEnd(assignBlock); | ||
| moore::BlockingAssignOp::create(builder, loc, lhs, value); | ||
| mlir::cf::BranchOp::create(builder, loc, continuedBlock); | ||
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| builder.setInsertionPointToEnd(continuedBlock); | ||
| } | ||
| return success(); |
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Nit: looks like an accidental deletion or rebase mishap.
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| struct Clog2BIOpConversion : public OpConversionPattern<Clog2BIOp> { | ||
| using OpConversionPattern::OpConversionPattern; | ||
| LogicalResult | ||
| matchAndRewrite(Clog2BIOp op, OpAdaptor adaptor, | ||
| ConversionPatternRewriter &rewriter) const override { | ||
| Value ceil_log; | ||
| auto len_in = adaptor.getValue().getType().getIntOrFloatBitWidth(); | ||
| auto tofloat = arith::UIToFPOp::create( | ||
| rewriter, op.getLoc(), rewriter.getF32Type(), adaptor.getValue()); | ||
| if (tofloat == 0) { | ||
| ceil_log = 0; | ||
| } else { | ||
| ceil_log = math::CeilOp::create( | ||
| rewriter, op.getLoc(), | ||
| math::Log2Op::create(rewriter, op.getLoc(), tofloat)); | ||
| } | ||
| Value out = arith::FPToUIOp::create( | ||
| rewriter, op.getLoc(), rewriter.getIntegerType(len_in), ceil_log); | ||
| rewriter.replaceOp(op, out); | ||
| return success(); | ||
| } | ||
| }; | ||
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Does the Arith dialect have some flavor of leading zero counting, such that we could implement this purely as an integer operation instead of casting to floats?
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This commit adds support for the System Verilog real math functions (IEEE1800-2017 Chapter 20.8) by adding previously missing patterns for conversion from Verilog to the 'moore' dialect and adds patterns for conversion using the MLIR dialects 'arith' and 'math' to allow the use of the real math functions as non-synthesizable constructs.
In combination with adding explicit conversion between int and real from the pull requests #9088 and #9317 this addresses the issue using the math functions as raised in issue #8930.
This is done by adding: