[LSQ] generation of both verilog and VHDL

data/rtl-config-verilog.json

@@ -905,9 +905,9 @@
   },
   {
     "name": "handshake.lsq",
-    "generator": "/usr/bin/env python3 $DYNAMATIC/tools/backend/lsq-generator-python/lsq-generator.py -o $OUTPUT_DIR -c $OUTPUT_DIR/$MODULE_NAME.json",
+    "generator": "/usr/bin/env python3 $DYNAMATIC/tools/backend/lsq-generator-python/lsq-generator.py -o $OUTPUT_DIR -c $OUTPUT_DIR/$MODULE_NAME.json --hdl verilog",
     "use-json-config": "$OUTPUT_DIR/$MODULE_NAME.json",
-    "hdl": "vhdl",
+    "hdl": "verilog",
     "io-kind": "flat",
     "io-map": [{ "clk": "clock" }, { "rst": "reset" }, { "*": "io_*" }],
     "io-signals": {

data/rtl-config-vhdl.json

@@ -55,7 +55,7 @@
   },
   {
     "name": "handshake.lsq",
-    "generator": "/usr/bin/env python3 $DYNAMATIC/tools/backend/lsq-generator-python/lsq-generator.py -o $OUTPUT_DIR -c $OUTPUT_DIR/$MODULE_NAME.json",
+    "generator": "/usr/bin/env python3 $DYNAMATIC/tools/backend/lsq-generator-python/lsq-generator.py -o $OUTPUT_DIR -c $OUTPUT_DIR/$MODULE_NAME.json --hdl vhdl",
     "use-json-config": "$OUTPUT_DIR/$MODULE_NAME.json",
     "hdl": "vhdl",
     "io-kind": "flat",
@@ -374,7 +374,7 @@
   },
   {
     "name": "handshake.lsq",
-    "generator": "/usr/bin/env python3 $DYNAMATIC/tools/backend/lsq-generator-python/lsq-generator.py -o $OUTPUT_DIR -c $OUTPUT_DIR/$MODULE_NAME.json",
+    "generator": "/usr/bin/env python3 $DYNAMATIC/tools/backend/lsq-generator-python/lsq-generator.py -o $OUTPUT_DIR -c $OUTPUT_DIR/$MODULE_NAME.json --hdl vhdl",
     "use-json-config": "$OUTPUT_DIR/$MODULE_NAME.json",
     "hdl": "vhdl",
     "io-kind": "flat",

tools/backend/lsq-generator-python/README.md

@@ -20,7 +20,7 @@ This Python-based LSQ generator generates the LSQ design outlined in Hailin Wang
 ### Sampele usage
 
 ```
-usage: lsq-generator.py [-h] [--output-dir OUTPUT_PATH] --config-file CONFIG_FILES
+usage: lsq-generator.py [-h] [--output-dir OUTPUT_PATH] --config-file CONFIG_FILES --hdl [vhdl|verilog]
 ```
 
 ### Sample json configuration file (Example: Histogram)
@@ -89,31 +89,27 @@ Configuration parameters needed for both chisel and Python based LSQ-generator c
 - **lsq-generator.py**  
   Runs the tool.
 
-- **vhdl_gen/**
+- **core_gen/**
   - **\_\_init__.py**  
     Re-exports a curated list of public API symbols (e.g. `main`, `generate`, `Logic`, `LSQ`).
 
-  - **cli.py**  
-    Parses command-line arguments (with `argparse`), converts them into a `Configs` instance, and calls the core generator.
-
   - **codegen.py**  
     Implements the `codeGen(config: Configs)` function.
 
   - **configs.py**  
     Defines the `Configs` class.
 
-  - **context.py**  
-    Defines the `VHDLContext` class. It substitutes the previous `global` VHDL context variables.
-
-  - **utils.py**  
-    - Defines `VHDLLogicType`, `VHDLLogicVecType`, `VHDLLogicTypeArray`, `VHDLLogicVecTypeArray`, `OpTab`.
-    - `IntToBits`, `Zero`, `GetValue`, `MaskLess`, `isPow2`, `log2Ceil` helper functions.
-    - Classes and functions need to be relocated into other files later.
+  - **ir.py**  
+    Defines the intermediate representation used to generate HDL
+    Defines  `Statement`, `Type`, `Val`, `BinOp`, `Bin`, `UnOp`, `Un`, `Bit`, `CustomStatement`, `WhenElse`.
 
   - **signals.py**  
     Defines the four signal classes:  `Logic`, `LogicVec`, `LogicArray`, `LogicVecArray`.
 
-  - **vhdlgen/operators/**  
+  - **utils.py**  
+    - Defines `GetValue`, `isPow2`, `log2Ceil` helper functions.
+
+  - **operators/**  
     Low-level functions that generate VHDL snippets:  
     - `assign.py`: `Op`  
     - `arithmetic.py`: `WrapAdd`, `WrapAddConst`, `WrapSub`
@@ -123,10 +119,17 @@ Configuration parameters needed for both chisel and Python based LSQ-generator c
     - `reduction.py`: `ReduceLogicVec`, `ReduceLogicArray`, `ReduceLogicVecArray`, `Reduce`
     - `shifts.py`: `RotateLogicVec`, `RotateLogicArray`, `RotateLogicVecArray`, `CyclicLeftShift`
 
-  - **vhdlgen/generators/**  
+  - **generators/**  
     High-level modules that build complete entities/architectures:  
     - `dispatchers.py` : `PortToQueueDispatcher`, `QueueToPortDispatcher`, `PortToQueueDispatcherInit`, `QueueToPortDispatcherInit`
     - `group_allocator.py` : `GroupAllocator`, `GroupAllocatorInit`
     - `lsq.py` : `LSQ`
+
+  - **emitters/**
+    Emitters used to emit either VHDL or Verilog code.
+    - `emmitter.py` : Abstract class `Emitter`
+    - `verilog_emitter.py` : `VerilogEmitter`
+    - `vhdl_emitter.py` : `VHDLEmitter`
+
 
 

tools/backend/lsq-generator-python/core_gen/__init__.py

@@ -0,0 +1,13 @@
+# core_gen/__init__.py
+from core_gen.configs import GetConfigs, Configs
+from core_gen.codegen import codeGen
+
+
+# from vhdlgen import *
+__all__ = [
+    # configs
+    "GetConfigs",
+    "Configs",
+    # codegen
+    "codeGen",
+]

tools/backend/lsq-generator-python/core_gen/codegen.py

@@ -0,0 +1,86 @@
+from core_gen.emitters import Emitter
+import core_gen.generators.group_allocator as group_allocator
+import core_gen.generators.dispatchers as dispatchers
+import core_gen.generators.lsq as lsq
+
+import core_gen.generators.lsq_submodule_wrapper as lsq_submodule_wrapper
+
+
+def codeGen(emitter: Emitter, path_rtl, configs):
+    # Initialize a wrapper object to hold all submodule generator instances.
+    lsq_submodules = lsq_submodule_wrapper.LSQ_Submodules()
+
+    name = configs.name + "_core"
+    # empty the file
+    file = open(f"{path_rtl}/{name}.{emitter.get_file_suffix()}", "w").close()
+
+    # Group Allocator
+    ga = group_allocator.GroupAllocator(name=name, suffix="_ga", configs=configs)
+    ga.generate(emitter.new(), path_rtl)
+    lsq_submodules.group_allocator = ga
+
+    # When the condition "if configs.numLdPorts > 0:" is not true:
+    # Do not generating dispatching modules when there are zero load ports.
+    #
+    # - WARNING: This logic needs more testing
+    # - TODO: Also remove the load queue when there are zero load ports.
+    if configs.numLdPorts > 0:
+        # Load Address Port Dispatcher
+        ptq_dispatcher_lda = dispatchers.PortToQueueDispatcher(
+            name,
+            "_lda",
+            configs.numLdPorts,
+            configs.numLdqEntries,
+            configs.addrW,
+            configs.ldpAddrW,
+        )
+        ptq_dispatcher_lda.generate(emitter.new(), path_rtl)
+        lsq_submodules.ptq_dispatcher_lda = ptq_dispatcher_lda
+
+        # Load Data Port Dispatcher
+        qtp_dispatcher_ldd = dispatchers.QueueToPortDispatcher(
+            name,
+            "_ldd",
+            configs.numLdPorts,
+            configs.numLdqEntries,
+            configs.dataW,
+            configs.ldpAddrW,
+        )
+        qtp_dispatcher_ldd.generate(emitter.new(), path_rtl)
+        lsq_submodules.qtp_dispatcher_ldd = qtp_dispatcher_ldd
+
+    # Store Address Port Dispatcher
+    ptq_dispatcher_sta = dispatchers.PortToQueueDispatcher(
+        name,
+        "_sta",
+        configs.numStPorts,
+        configs.numStqEntries,
+        configs.addrW,
+        configs.stpAddrW,
+    )
+    ptq_dispatcher_sta.generate(emitter.new(), path_rtl)
+    lsq_submodules.ptq_dispatcher_sta = ptq_dispatcher_sta
+
+    # Store Data Port Dispatcher
+    ptq_dispatcher_std = dispatchers.PortToQueueDispatcher(
+        name,
+        "_std",
+        configs.numStPorts,
+        configs.numStqEntries,
+        configs.dataW,
+        configs.stpAddrW,
+    )
+    ptq_dispatcher_std.generate(emitter.new(), path_rtl)
+    lsq_submodules.ptq_dispatcher_std = ptq_dispatcher_std
+
+    # Store Backward Port Dispatcher
+    if configs.stResp:
+        qtp_dispatcher_stb = dispatchers.QueueToPortDispatcher(
+            name, "_stb", configs.numStPorts, configs.numStqEntries, 0, configs.stpAddrW
+        )
+        qtp_dispatcher_stb.generate(emitter.new(), path_rtl)
+        lsq_submodules.qtp_dispatcher_stb = qtp_dispatcher_stb
+
+    # Change the name of the following module to lsq_core
+    lsq_core = lsq.LSQ(name, "", configs)
+    lsq_core.generate(emitter, lsq_submodules, path_rtl)

tools/backend/lsq-generator-python/core_gen/configs.py

@@ -0,0 +1,134 @@
+#
+# Dynamatic is under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+
+import math
+import json
+import sys
+
+# read and parse the json file
+# example json format in README
+
+
+def GetConfigs(config_json_path: str):
+    with open(config_json_path, "r") as file:
+        configString = file.read()
+        configs = json.loads(configString)
+        return Configs(configs)
+
+
+class Configs:
+    """
+    Configuration object for LSQ code generation.
+
+    This class is instantiated using 'GetConfigs(path_to_json_file)', which loads a JSON file
+    and overwrites all the values below using user-defined parameters.
+
+    The values shown below are NOT the actual values used during generation;
+    they are one of possible default configurations.
+    """
+
+    name: str = "test"  # Name prefix used for generated VHDL files
+    dataW: int = 16  # Data width        (Number of bits for load/store data)
+    addrW: int = 13  # Address width     (Number of bits for memory address)
+    idW: int = 2  # ID width          (Number of bits for ID in the memory interface)
+    numLdqEntries: int = 3  # Load queue size   (Number of entries in the load queue)
+    numStqEntries: int = 10  # Store queue size  (Number of entries in the store queue)
+    numLdPorts: int = 3  # Number of load access ports
+    numStPorts: int = 3  # Number of store access ports
+    numGroups: int = 2  # Number of total Basic Blocks (BBs)
+    numLdMem: int = 1  # Number of load channels at memory interface (Fixed to 1)
+    numStMem: int = 1  # Number of store channels at memory interface (Fixed to 1)
+
+    gaNumLoads: list = [2, 1]  # Number of loads in each BB
+    gaNumStores: list = [2, 1]  # Number of stores in each BB
+    gaLdOrder: list = [
+        [2, 2],  # The order matrix for each group
+        [0],
+    ]  # Outer list (Row): Index for each BB
+    # Inner list (Column): List of store counts ahead of each load
+    # In this example -> BB0=[st0,st1,ld0,ld1], BB1=[ld2,st2]
+    gaLdPortIdx: list = [
+        [0, 1],  # The related access port index for each load in BB
+        [2],
+    ]
+    gaStPortIdx: list = [
+        [0, 1],  # The related access port index for each store in BB
+        [2],
+    ]
+    ldqAddrW: int = 2  # Load queue address width
+    stqAddrW: int = 4  # Store queue address width
+    ldpAddrW: int = 2  # Load port address width
+    stpAddrW: int = 2  # Store port address width
+
+    pipe0: bool = False  # Enable pipeline register 0
+    pipe1: bool = False  # Enable pipeline register 1
+    pipeComp: bool = False  # Enable pipeline register pipeComp
+    headLag: bool = False  # Whether the head pointer of the load queue is updated
+    # one cycle later than the valid bits of entries
+    stResp: bool = (
+        False  # Whether store response channel in store access port is enabled
+    )
+    gaMulti: bool = (
+        False  # Whether multiple groups are allowed to request an allocation at the same cycle
+    )
+
+    def __init__(self, config: dict) -> None:
+        self.name = config["name"]
+        self.dataW = config["dataWidth"]
+        self.addrW = config["addrWidth"]
+        self.idW = config["indexWidth"]
+        self.numLdqEntries = config["fifoDepth_L"]
+        self.numStqEntries = config["fifoDepth_S"]
+        self.numLdPorts = config["numLoadPorts"]
+        self.numStPorts = config["numStorePorts"]
+        self.numGroups = config["numBBs"]
+        self.numLdMem = config["numLdChannels"]
+        self.numStMem = config["numStChannels"]
+        self.master = bool(config["master"])
+
+        self.stResp = bool(config["stResp"])
+        self.gaMulti = bool(config["groupMulti"])
+
+        self.gaNumLoads = config["numLoads"]
+        self.gaNumStores = config["numStores"]
+        self.gaLdOrder = config["ldOrder"]
+        self.gaLdPortIdx = config["ldPortIdx"]
+        self.gaStPortIdx = config["stPortIdx"]
+
+        self.ldqAddrW = math.ceil(math.log2(self.numLdqEntries))
+        self.stqAddrW = math.ceil(math.log2(self.numStqEntries))
+
+        # Original empty assignment assumes the size of load or store queue to be always a multiple of 2
+        if self.numLdqEntries & (self.numLdqEntries % 2 == 0):
+            self.emptyLdAddrW = math.ceil(math.log2(self.numLdqEntries + 1))
+        else:
+            self.emptyLdAddrW = math.ceil(math.log2(self.numLdqEntries)) + 1
+
+        if self.numStqEntries & (self.numStqEntries % 2 == 0):
+            self.emptyStAddrW = math.ceil(math.log2(self.numStqEntries + 1))
+        else:
+            self.emptyStAddrW = math.ceil(math.log2(self.numStqEntries)) + 1
+        # Check the number of ports, if num*Ports == 0, set it to 1
+        self.ldpAddrW = math.ceil(
+            math.log2(self.numLdPorts if self.numLdPorts > 0 else 1)
+        )
+        self.stpAddrW = math.ceil(
+            math.log2(self.numStPorts if self.numStPorts > 0 else 1)
+        )
+
+        self.pipe0 = bool(config["pipe0En"])
+        self.pipe1 = bool(config["pipe1En"])
+        self.pipeComp = bool(config["pipeCompEn"])
+        self.headLag = bool(config["headLagEn"])
+
+        assert self.idW >= self.ldqAddrW
+
+        # list size checking
+        assert len(self.gaNumLoads) == self.numGroups
+        assert len(self.gaNumStores) == self.numGroups
+        assert len(self.gaLdOrder) == self.numGroups
+        assert len(self.gaLdPortIdx) == self.numGroups
+        assert len(self.gaStPortIdx) == self.numGroups

tools/backend/lsq-generator-python/core_gen/emitters/__init__.py

@@ -0,0 +1,6 @@
+# core_gen/emitters/__init__.py
+from core_gen.emitters.emitter import Emitter
+from core_gen.emitters.vhdl_emitter import VHDLEmitter
+from core_gen.emitters.verilog_emitter import VerilogEmitter
+
+__all__ = ["Emitter", "VHDLEmitter", "VerilogEmitter"]