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[LSQ] generation of both verilog and VHDL#914

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JasmijnB wants to merge 98 commits into
EPFL-LAP:mainfrom
JasmijnB:lsq-verilog
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[LSQ] generation of both verilog and VHDL#914
JasmijnB wants to merge 98 commits into
EPFL-LAP:mainfrom
JasmijnB:lsq-verilog

Add bool_to_logic to vhdl emitter

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