Add ADC DMA block acquisition

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Goal

Move ADC samples into memory using DMA so the CPU does not process every conversion individually.

This should establish block-based acquisition suitable for higher sampling rates.

Target Architecture

Timer
  ↓
ADC
  ↓
DMA
  ↓
sample buffer

Tasks

• Configure ADC DMA transfers.
• Allocate a fixed-size sample buffer.
• Start continuous or block-based DMA acquisition.
• Avoid per-sample interrupts.
• Track DMA completion/error events.
• Add diagnostic counters for:
  • completed blocks
  • DMA errors
  • acquisition errors
• Verify DMA-accessible memory placement.
• Investigate STM32H753 cache coherency requirements.
• Document the chosen memory/cache strategy.

STM32H7 Requirement

The STM32H753 uses a Cortex-M7 with data cache and multiple RAM domains.

Do not assume DMA/CPU cache coherency automatically works.

Explicitly determine:

• which DMA controller is used
• where the buffer is placed
• whether that RAM is DMA-accessible
• whether D-cache covers the region
• whether cache clean/invalidate operations are required
• whether buffer alignment matters

Acceptance Criteria

• ADC samples are transferred using DMA.
• CPU does not receive one interrupt per ADC sample.
• Completed DMA blocks contain valid ADC samples.
• DMA errors are detectable.
• Buffer memory placement is documented.
• Cache/coherency behavior is documented.
• No unexplained corruption is observed during hardware testing.