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[Backend][BLIF] Automatic generation of blif files #872
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dbb2e8b
Added yosys into compilation flow of dynamatic
Carmine50 f78eff5
Fixed bug in terminator ordering operations
Carmine50 885654f
Added extra attribute when flattening to record the original module t…
Carmine50 9937989
Fixed bug using dense set
Carmine50 cccfb4f
Added BLIF Generator
Carmine50 f74db1e
Added doc for blif generator
Carmine50 922b748
Added online blif generator
Carmine50 b08ecef
Integrated online generation in the blif file manager
Carmine50 74ac113
Removed unused function
Carmine50 543bf1c
Merge branch 'main' into feature/crizzi/automatic-blif-generation
Carmine50 bf9d691
Merge branch 'main' into feature/crizzi/automatic-blif-generation
Carmine50 219b3a7
Added parameters for RTL generation inside tablegen for each handshak…
Carmine50 806869d
Fixed bug in terminator ordering operations
Carmine50 d87fc57
Updated BLIF generator to use the RTL generator
Carmine50 ecda7db
Added RTL generator
Carmine50 563fbe8
Added RTL generator
Carmine50 cf67cd6
Updated BLIF File Manager with new params retrieval
Carmine50 ed7a46e
Updated BLIF File Manager with new params retrieval
Carmine50 547ad97
Merge branch 'main' into feature/crizzi/automatic-blif-generation
Carmine50 5d62f28
Added enable yosys flag to unittest
Carmine50 de85461
Fixed format
Carmine50 c304b88
Added unittest for BLIFFileManager
Carmine50 83dbd32
Added more inputs to the mark pass
Carmine50 7d6bcfe
Added dynamatic root and RTL json file as inputs parameter
Carmine50 85e585d
Changed input name formatting
Carmine50 f77a8e0
Replaced RTL and BLIF generator with a backend generator
Carmine50 001e738
Fixed typo
Carmine50 f7de867
Changed doc from BLIF generator to backend generator
Carmine50 4582dd2
Fixed formatting issue
Carmine50 c8ed4ca
Fixed typo
Carmine50 5539676
Removed abc and yosys executable as inputs and directly used in the r…
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99 changes: 99 additions & 0 deletions
99
docs/DeveloperGuide/DynamaticFeaturesAndOptimizations/Synth/BLIFGenerator.md
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| # BLIFGenerator | ||
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| ## Overview | ||
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| `BLIFGenerator` is a C++ class that synthesises a BLIF file on demand for a given Handshake component by invoking **Yosys** (synthesis) followed by **ABC** (logic optimisation). It replicates the logic of `tools/blif-generator/blif_generator.py` and is called automatically by `BLIFFileManager` when a required BLIF file is not yet present on disk. | ||
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| The generator requires `DYNAMATIC_ENABLE_ABC` and `DYNAMATIC_ENABLE_YOSYS` to be enabled at build time (see [CMake configuration](#cmake-configuration)). | ||
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| --- | ||
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| ## Synthesis Pipeline | ||
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| For each component, generation proceeds in the following steps: | ||
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| 1. **JSON config lookup**: The component name is looked up in `data/rtl-config-verilog.json` to obtain the Verilog source file(s) and the names of the parameterisable generics. | ||
| 2. **Verilog generation**: If the JSON entry has a `generator` command instead of a static `generic` file, the generator is executed first to produce the Verilog. | ||
| 3. **Dependency collection**: All Verilog files listed under `dependencies` are collected recursively. | ||
| 4. **Yosys synthesis**: A `run_yosys.sh` script is written to the output directory and executed. It uses `chparam` to set the generic values, then synthesises to BLIF. | ||
| 5. **ABC optimisation**: A `run_abc.sh` script applies a multi-iteration rewrite/refactor sequence (`strash` + 6x (`rewrite`; `balance`; `refactor`; `balance`)) and writes the optimised BLIF. | ||
| 6. **Blackbox post-processing**: For components whose internal logic should remain abstract, `.names` / `.latch` lines are stripped from the output BLIF. | ||
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| --- | ||
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| ## Output Directory Layout | ||
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| Generated files are placed under `<blifDirPath>/<component>/<param1>/<param2>/`: | ||
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| ``` | ||
| <blifDirPath>/ | ||
| <component>/ | ||
| <param1>/ | ||
| <param2>/ | ||
| <component>_<param1>_<param2>_yosys.blif <- raw Yosys output | ||
| <component>.blif <- final ABC-optimised output | ||
| run_yosys.sh <- synthesis script | ||
| run_abc.sh <- optimisation script | ||
| ``` | ||
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| The path follows the same convention used by `BLIFFileManager::combineBlifFilePath`. | ||
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| --- | ||
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| ## JSON Config Lookup | ||
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| The generator reads `data/rtl-config-verilog.json` (located two levels above `blifDirPath`) to find the entry for the requested component. The lookup priority for matching an entry is: | ||
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| 1. `module-name` field (exact match) | ||
| 2. `name` field with the `"handshake."` prefix stripped | ||
| 3. Basename of the `generic` file path (for support modules without a `name`) | ||
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| --- | ||
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| ## Parameter Mapping | ||
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| The JSON `parameters` array may contain a mix of fixed and range (generic) parameters. Only **range parameters** contribute to the Yosys `chparam` command and to the BLIF path. A parameter is a range parameter when: | ||
| - Its `type` is `"unsigned"` or `"dataflow"`, **and** | ||
| - It has no `eq` or `data-eq` fixed-value constraint, **and** | ||
| - Its `generic` field is not explicitly `false`. | ||
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| The `paramValues` passed to `generate()` are **right-aligned** against the ordered list of range parameter names. This means a single value always maps to the innermost (last) range parameter, which is correct for components like `tfifo` where the BLIF path encodes only `DATA_TYPE` but the JSON also declares `NUM_SLOTS` as a range parameter. | ||
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| --- | ||
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| ## Key Functions | ||
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| ### Constructor | ||
| ```cpp | ||
| BLIFGenerator(const std::string &blifDirPath, | ||
| const std::string &yosysExecutable, | ||
| const std::string &abcExecutable); | ||
| ``` | ||
| - `blifDirPath`: absolute path to the BLIF file tree (e.g. `<repo>/data/blif`). The Dynamatic root and the JSON config path are derived from this. | ||
| - `yosysExecutable` / `abcExecutable`: paths to the Yosys and ABC binaries. | ||
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| --- | ||
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| ### `generate` | ||
| ```cpp | ||
| bool generate(const std::string &component, | ||
| const std::vector<std::string> ¶mValues); | ||
| ``` | ||
| Runs the full synthesis pipeline for the given component and parameter values. Returns `true` if `<component>.blif` exists in the output directory after generation. | ||
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| `component` must match the JSON `module-name` (or the stripped `name`) of the target entry, e.g. `"addi"`, `"fork_dataless"`, `"oehb"`. | ||
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| --- | ||
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| ## CMake Configuration | ||
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| `BLIFGenerator` is only active when both `DYNAMATIC_ENABLE_ABC=ON` and `DYNAMATIC_ENABLE_YOSYS=ON` are passed to CMake (e.g. via `./build.sh --enable-abc --enable-yosys`). These options: | ||
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| 1. Build ABC and Yosys as CMake `FetchContent` dependencies. | ||
| 2. Set `DYNAMATIC_ABC_EXECUTABLE` and `DYNAMATIC_YOSYS_EXECUTABLE` CMake variables to the built binary paths. | ||
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| In `BLIFFileManager`, the call to `BLIFGenerator` is guarded by: | ||
| ```cpp | ||
| #if defined(DYNAMATIC_YOSYS_EXECUTABLE) && defined(DYNAMATIC_ABC_EXECUTABLE) | ||
| ``` | ||
| If neither macro is defined, a missing BLIF file causes an assertion failure with a message directing the user to enable those options. |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,62 @@ | ||
| //===- BLIFGenerator.h - On-demand BLIF file generator ----------*- C++ -*-===// | ||
| // | ||
| // Dynamatic is under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| // | ||
| // Generates a BLIF file for a given Handshake operation by running Yosys | ||
| // (synthesis) followed by ABC (optimization). | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
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| #ifndef DYNAMATIC_SUPPORT_BLIFGENERATOR_H | ||
| #define DYNAMATIC_SUPPORT_BLIFGENERATOR_H | ||
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| #include "mlir/IR/Operation.h" | ||
| #include <string> | ||
| #include <vector> | ||
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| namespace dynamatic { | ||
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| class BLIFGenerator { | ||
| public: | ||
| BLIFGenerator(const std::string &blifDirPath, | ||
| const std::string &dynamaticRootPath, | ||
| const std::string &RTLJSONFile, | ||
| const std::string &yosysExecutable, | ||
| const std::string &abcExecutable, mlir::Operation *op, | ||
| const std::string &expectedBlifPath); | ||
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| /// Generate the BLIF file for the operation supplied at construction. | ||
| /// | ||
| /// If the expected BLIF file already exists, this function does nothing and | ||
| /// returns true. Otherwise, it runs the RTL generator, Yosys, and ABC in | ||
| /// sequence to produce the BLIF file. | ||
| /// | ||
| /// Returns true when the BLIF file was successfully created. | ||
| bool generate(); | ||
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| private: | ||
| std::string blifDirPath; /// Absolute path to the BLIF directory. | ||
| std::string RTLJSONFile; /// Path to the RTL JSON configuration file. | ||
| std::string dynamaticRoot; /// Dynamatic root, derived from blifDirPath. | ||
| std::string yosysExecutable; /// Path to the Yosys binary. | ||
| std::string abcExecutable; /// Path to the ABC binary. | ||
| mlir::Operation *op; /// The operation to synthesize. | ||
| std::string expectedBlifPath; /// Expected output path of the final BLIF. | ||
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| /// Write run_yosys.sh inside outputDir and execute it. | ||
| bool runYosys(const std::string &topModule, const std::string &outputDir, | ||
| const std::vector<std::string> &verilogFiles, | ||
| const std::string &outputName) const; | ||
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| /// Write run_abc.sh inside outputDir and execute it. | ||
| bool runAbc(const std::string &inputFile, const std::string &outputDir, | ||
| const std::string &outputName) const; | ||
| }; | ||
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| } // namespace dynamatic | ||
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| #endif // DYNAMATIC_SUPPORT_BLIFGENERATOR_H |
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| Original file line number | Diff line number | Diff line change |
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| //===- RTLGenerator.h - RTL code generator from JSON config -----*- C++ -*-===// | ||
| // | ||
| // Dynamatic is under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| // | ||
| // Generates a Verilog file for a given Handshake operation by looking up its | ||
| // entry in a JSON RTL config, substituting RTL parameters, and running the | ||
| // configured generator command. | ||
| // | ||
| // Parameters are extracted from the operation via RTLAttrInterface | ||
| // (getRTLParameters()). Results (module name, output directory, Verilog file | ||
| // list) are available via getters after a successful generate() call. | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
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| #ifndef DYNAMATIC_SUPPORT_RTLGENERATOR_H | ||
| #define DYNAMATIC_SUPPORT_RTLGENERATOR_H | ||
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| #include <string> | ||
| #include <vector> | ||
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| namespace mlir { | ||
| class Operation; | ||
| } // namespace mlir | ||
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| namespace dynamatic { | ||
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| class RTLGenerator { | ||
| public: | ||
| RTLGenerator(const std::string &rtlConfigPath, | ||
| const std::string &dynamaticRoot, | ||
| const std::string &outputBaseDir, mlir::Operation *op); | ||
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| /// Runs the RTL generator command found in the JSON config. | ||
| /// | ||
| /// Extracts parameters from the operation via RTLAttrInterface, locates the | ||
| /// matching config entry, substitutes all variables into the generator | ||
| /// command, and executes it. On success the generated and support Verilog | ||
| /// files are collected and made available via getters. | ||
| /// | ||
| /// Returns true when RTL generation succeeded. | ||
| bool generate(); | ||
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| const std::string &getModuleName() const { return moduleName; } | ||
| const std::string &getOutputDir() const { return outputDir; } | ||
| const std::vector<std::string> &getVerilogFiles() const { | ||
| return verilogFiles; | ||
| } | ||
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| private: | ||
| std::string rtlConfigPath; /// Absolute path to the JSON RTL config file. | ||
| std::string dynamaticRoot; /// Project root used to resolve $DYNAMATIC paths | ||
| /// in the config. | ||
| std::string outputBaseDir; /// Base directory under which the per-module | ||
| /// output subdirectory will be created. | ||
| mlir::Operation *op; /// The Handshake operation to generate RTL for. | ||
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| std::string moduleName; /// The generated module name, derived from the | ||
| /// operation name and parameters. | ||
| std::string outputDir; /// The output directory for generated files, derived | ||
| /// from outputBaseDir, operation name, and parameters. | ||
| std::vector<std::string> | ||
| verilogFiles; /// List of generated and support Verilog files to be | ||
| /// synthesized, including the main generated file | ||
| /// (outputDir/moduleName.v) and any additional files | ||
| /// specified in the config with "generic" paths. | ||
| }; | ||
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| } // namespace dynamatic | ||
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| #endif // DYNAMATIC_SUPPORT_RTLGENERATOR_H | ||
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why does this still need RTL config?