[vhdl] Fix incorrect latency of 64-bit cmpf

[zero9178]

The components.json file previously denoted cmpf to have a latency of 0 which the unit generator for cmpf also hardcoded.

While this is the case for 32-bit, this is incorrect for FloPoCo on 64-bit (Line 3940 in flopoco_ip_cores.vhd):

--------------------------------------------------------------------------------
--                             FPComparator_64bit
--                       (FPComparator_11_52_F500_uid2)
-- VHDL generated for Kintex7 @ 500MHz
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Florent de Dinechin (2021)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
-- Clock period (ns): 2
-- Target frequency (MHz): 500
-- Input signals: X Y
-- Output signals: unordered XltY XeqY XgtY XleY XgeY

Worse than that, the unordered and XeqY have a latency of 0 while the other flags have a latency of 1, meaning it is inconsistent dependeing on the predicate of cmpf.

We cannot currently model different predicates having different latencies in the components.json.
This PR therefore fixes the issue by just correcting the components.json entry and the unit-generator for the non-0 latency case, and adding an extra cycle of latency for unordered and XeqY to have a consistent latency regardless of predicate.

Fixes #860
Fixes #999
Fixes #949
Fixes #1003