quartus-prime

Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.

fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification

Updated Jun 22, 2026
VHDL

Jefferson-Lopes / quartus-installation

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Full tutorial about how to install Quartus Prime software in different systems

ubuntu installation quartus-prime quartus-linux

Updated Nov 8, 2024

MinatsuT / CYC1000_SDRAM

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A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000

Updated Jul 8, 2021
Verilog

peter-tanner / Intel-Quartus-Dark-Mode-Windows

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A script to convert the Intel Quartus IDE to dark mode using QDarkStyleSheet with some modifications.

theme fpga dark-theme ide intel dark-mode quartus-prime quartus

Updated Aug 10, 2024
PowerShell

tharinduSamare / Multicore_processor_verilog_design

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This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.

fpga simulation verilog modelsim quartus-prime

Updated Jan 8, 2022
Verilog

WassimHedfi / FPGA-Projects

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This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.

c fpga vhdl verilog modelsim quartus-prime de10-lite fpga-design programmable-logic-design softcore-processor-design

Updated Sep 26, 2024
Verilog

Nathen-Smith / FPGA-super-mario-bros

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FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

systemverilog fpga-soc quartus-prime nios2

Updated Dec 16, 2021
Verilog

robseb / socfpgaPlatformGenerator

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Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

build-automation linux-distribution u-boot quartus-prime cyclone-v sd-card-image intel-fpga arria10 soc-fpgas soc-eds

Updated Jun 4, 2024
Python

egk696 / EDAC_SDRAM_Controller

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Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

fpga vhdl embedded-systems vivado fault-tolerant quartus-prime sdram sdram-controller cots-sdram

Updated Oct 30, 2017
Verilog

meetdoshi90 / 8-Bit-RISC-Microprocessor

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An 8-bit RISC based processor designed in verilog with x86 instructions.

cpu fpga verilog x86 microprocessor modelsim 8-bit quartus-prime risc-processor 8-bit-computer

Updated Sep 6, 2021

Paebbels / pyIPCMI

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A Python-based IP Core Management Infrastructure.

infrastructure database simulation vhdl intel python3 xilinx synthesis altera modelsim questasim xilinx-vivado quartus-prime vhdl-verification ip-core riviera-pro

Updated Apr 29, 2021
Python

pa-tiq / vending_machine

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fpga verilog quartus-prime quartus de10nano de10-lite de10-nano verilog-project quartus-18-1

Updated Jul 14, 2019
Verilog

yuravg / eda-scripts

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Collection of scripts for EDA tools

fpga questasim quartus-prime quartus

Updated Feb 3, 2026
Shell

MohamedHussein27 / RISC-V-Single-Cycle-Implementation

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This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book.

vivado computer-architecture digital-design quartus-prime verilog-project rtl-design

Updated Jan 1, 2025
Verilog

jagumiel / irReceiver

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FPGA-based Sony SIRC infrared receiver and pulse-width decoder in VHDL for the Terasic DE1-SoC, featuring an FSM, LED output and testbench.

vhdl ir-receiver quartus-prime ir-decoder vhdl-code infrared-decoder sony-sirc-protocol

Updated Jul 30, 2026
VHDL

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