This release has been tested with Chisel 3.5, 3.6, 5, and 6.
It contains an additional chapter on a pipelined RISC-V processor and a further appendix on comparing VHDL and Verilog.
New Contributors
- @Emoun made their first contribution in #48
- @MrAMS made their first contribution in #58
- @keszocze made their first contribution in #63
- @donaldkuck made their first contribution in #64
Full Changelog: v5.0...v6.0
Contributors
keszocze, MrAMS, and 2 other contributors