A ISA slot card PC/AT minimal test design featuring a Cyclone II FPGA. A completely integrated PC/AT mainboard design using the 80286 CPU featuring a Cyclone II FPGA which contains the core logic and HDL versions of the core PC/AT controllers.
Keep an eye out at the bottom for the latest developments!
This project was created for historical purposes out of love for historical computing designs and for the purpose of enabling computing enthousiasts with a sufficient level of building and troubleshooting expertise to be able to experience the technology by building and troubleshooting the hardware described in this project. Due to the level of this project, it may be suitable as a project for students to get into. If there are any questions from teachers who like to teach about this technology I would be happy to answer them. It may be really interesting to analyse the elaborate and complex CPU timing and 8 bit to 16 bit data byte translation and DMA mechanisms in an educational setting.
Besides the GPL3 license there are a few warnings and usage restrictions applicable: No guarantees of function or fitness for any particular or useful purpose is given, building and using this design is at the sole responsibility of the builder.
Do not attempt this project unless you have the necessary electronics assembly expertise and experience, and know how to observe all electronics safety guidelines which are applicable.
It is not permitted to use the computer built from this design without the assumption of the possibility of loss of data or malfunction of the connected device. To be used strictly for personal hobby and experimental purposes only. No applications are permitted where failure of the device could result in damage or injury of any kind.
If you plan to use this design or any part of it in new designs, the acknowledgement of the designer and the design sources and inspirations, historical and modern, of all subparts contained within this design should be included and respected in your publication, to accredit the hard work, time and effort dedicated by the people before you who contributed to make your project possible.
No guarantee for any proper operation or suitability for any possible use or purpose is given, using the resulting hardware from this design is purely educational and experimental and not intended for serious applications. Loss of data is likely and to be expected when connecting any storage device or storage media to the resulting system from this design, or when configuring or operating any storage device or media with the system of this design.
When connecting this system to a computer network which contains stored information on it, it is at the sole responsibility and risk of the person making the connection, no guarantee is given against data loss or data corruption, malfunctions or failure of the whole computer network and/or any information contained inside it on other devices and media which are connected to the same network.
When building this project, the builder assumes personal responsibility for troubleshooting it and using the necessary care and expertise to make it function properly as defined by the design. You can email me with questions, but I will reply only if I have time and if I find the question to be valid. Which will probably also lead to an update here. I want to primarily dedicate my time to new project development, I am not able to do any user support, so that's why I provide the elaborate info here which will be expanded if needed.
Special thanks to
- sqpat for his essential support of all my PC/AT related work! And of course for his work on the RealDOOM project!
- kevju on the VCF forum for giving me some useful time-saving FPGA tips about various topics including the usage of FET based bus switch and level conversion ICs and very helpful BGA PCB layout tips, FPGA power regulators.
- marshallh on the VCF forum for giving me a lot of additional advice regarding FPGAs and Altera Cyclone chips, configuring the FPGA, usage of flash configuration ICs, and more.
- IBM corporation - the PC team led by Don Estridge
- Intel corporation for creating these awesome legacy processors without which the PC/AT would not have existed!
- see the PC/AT V1 project for many more people who all gave their support and inspired me greatly!
- costastep here on GitHub for providing useful ideas and background, see the "issue" thread
- htminuslab (Hans Tiggeler) for creating such clear and transparent examples of the core AT controllers in HDL which inspired a lot of confidence on closer look at the code
Also a special thanks goes out to user LimeProgramming (Adam) here on GitHub for making his excellent USB to serial mouse project with the RP2040! https://github.com/LimeProgramming/USB-serial-mouse-adapter He kindly agrees for his project to be integrated into mine in a modified form, thank you Adam!
Thanks to sqpat for the friendly discussions and resulting joint effort to develop the REV3D EMS system and driver written by sqpat, now fully supporting RealDOOM, and to be continued here in the REV4 FPGA system of course. I thank sqpat for sending me more clock speed verified Harris 286 CPUs to use in the projects, and several PC/AT chipset mainboards for testing and evaluation. Do remember to check out his project RealDoom here on GitHub!
Acknowledgements of people who were instrumental in preceeding developments upon which this design was elaborated:
Don Estridge
IBM PC development team
Some historical info
Bill Lowe
XT-IDE universal BIOS project development team for developing the XT-IDE BIOS
Amazing and extremely efficient software, fast disk access for XT and various AT computers.
Works with every IDE drive I have tested. Still under active development earlier in 2023.
All source data remains the copyright of the original creators and must be respected.
This design is only released for hobby computing enthousiasts and educational purposes, no profit is to be made from this design or derived work from it.
This project is the 4th revision of my PC/AT development work, which started out by the REV1 recreation and reverse engineering work to rebuild a PC/AT based on the IBM 5170 using CPLD technology.
I then proceeded to develop system control replacement in the CPLDs, extensively rewiring the REV1 PCB, after which I then assembled REV2 intermediate designs to reflect all the developed improvements and upgrades.
I then decided to release a final CPLD based mainboard project, the REV3D system, also fully featured here on GitHub.
Using CPLDs for this project was both frustrating and difficult because of logic limitations, however I finally managed to do it!
So the REV3D system reflects a really stable and almost fully integrated complete implementation of a 80286 based PC/AT based on the IBM 5170, which now is able to run at 22.4MHz, including to run windows and RealDOOM as created by sqpat and featured here on GitHub.
Recommended VGA card is a cirrus logic, if possible a Diamond Speedstar pro.
After finalizing the REV3D project by supporting to run RealDOOM on the system with the kind assistance of sqpat here on GitHub, I have conceived a fully integrated PC/AT system which implemented all the bus logic inside the 5 CPLD chips on the REV3D board. The resulting design created a rock solid stable PC mainboard and serves as the preparation basis for now developing this FPGA stage design.
As described in the REV4 FPGA based full mainboard design project, I proceeded to assemble a complete quartus project which contains all the logic of the REV3D PC/AT project with several enhancements. Since this is my first FPGA project there were a few unclear things and talking with kevju on the VCF forum he gave me the idea to create a test PCB to test a few things.
The main issue as the AS configuration flash connection with the USB blaster programmer. The documentation from different sources was showing inconsistent information.
This made it unclear how to connect the configuration circuits with the Cyclone II 572 pin BGA.
So I searched for some development systems featuring the Cyclone II in smaller packages, where I found a 5000LE version. However I wanted to include a larger capacity for an affordable price, which turned out to be the EPM7256SQC208.
I am currently designing an ISA slot card which can feature a complete but minimal PC/AT system, besides that purpose, the PCB will also be capable of being built up as a development board where we have four 40 pin headers to plug in flatcable connectors that can wire the test card into any type of circuit for testing and development of other logic.
In addition I may attempt to enable the card to feature some form of VGA controller interface by leaving out the 286 CPU and using those pins for the VGA output. The connector is already added to the card but I still need to work out more details and see if this is feasible.
After finishing this design I will order the PCBs and build up a test system.
Basically the test system is meant to function equivalently as a bare mainboard system where there are no integrated IO besides the core PC/AT mainboard function and memory.
The system will be able to be plugged into a ISA backplane to form a PC system by adding ISA slot cards.
Possibly I will design a ISA backplane with ATX power to make it easier to test the card based test system.
The system may possibly be limited how many slot cards are able to be added since the driving current is 24mA per pin.
The FPGA will be a pin reduced version where we try to get the most capability out of a smaller number of pins (208 pin package).
This project has evolved from the IBM 5170 reverse engineering work. Also we try to remain as faithful to the 5170 concept as possible, while at the same time not limit ourselves, and rather finding a suitable balance to enhance the system and reduce limitations. The idea is to form a fast 286 system with all the typical features you would want for DOS applications and games.
The core PC/AT controllers are featured as HDL modules which are then wired into the complete PC/AT block design.
So the system structure is meant to remain clearly visible and recognizable in the block design linking all the logic together, rather than resorting to pure HDL code based design.
Tests will need to indicate whether this is possible to function correctly because quartus support for HDL block modules may have some issues though uncertain because this will be the first FPGA based project.
Also we will attempt to increase the 286 clock speed and efficiency. This work is started here for verification on this test card, and then after a lot of things are tested and confirmed, we will continue with the intended project, the full mainboard design based on the BGA FPGA.
A larger BGA FPGA chip is necessary to allow the system to develop much further to allow the 286 to make use of a larger capacity BGA. Also with more pins we can feature a separate memory bus which can follow alternative timing. In addition we will look at PCI bus support for a 286 if this could be achieved.
Further details can be found in the REV4 full mainboard sized project.
The same core AT controllers found in the full mainboard project will be included here in the ISA test card design:
htminuslab - Hans Tiggeler:
HTL8237
HTL8259
HTL8254
HTL146818
ao486 project - Aleksander Osman:
AO486 - PS2 keyboard/mouse controller (to be verified with MR BIOS!)
Please note: above controllers will need to be tested and debugged before we can confirm the system will be able to fully function with them.
So nothing is verified yet, the information outlines the design approach.
This ISA card project will serve as a test platform to proceed with more certainty in the full mainboard sized project. In a worst case scenario, this project can still verify:
- AS configuration and flashing circuits to be fully functional
- individual core PC/AT controllers can be programmed on the card and wired into a suitable PC/AT system for separate testing and verification to confirm them to be suitable to be used to support an actual PC/AT system. Test system may be the REV1 CPLD project or possibly the IBM 5170 mainboard.
More details will follow as this ISA card based 286 system will be developed first now in preparation of the REV4 mainboard.
- The FPGA is a 208 pin QFP package
- There will be 6 1MB SRAMs on the card
- the card will feature a 8 bit ROM
- in FPGA project we will attempt to load the system ROM code from the serial AS flash chip and shadow copy it into RAM.
- the card design will attempt to feature EMS RAM supporting the RealDOOM project by sqpat here on GitHub.
- all FPGA pins will be routed through bus switches making the IO pins capable of interfacing with 5V logic
Currently the 208 pin FPGA project is able to fully compile and a possibly suitable pin assigment has been found and confirmed to at least compile in quartus. So having the pin assignments I can proceed to create the part in KiCad and work on developing the PCB layout. A few small matters need to be sorted out which I will do shortly.
Thank you to all visitors here and in my other PC/AT projects for your interest in reading this project description, more details will follow on this page as soon as I have them!
From july 2026 I will only update my project blog on my own website and I will update the readme info on GitHub for the projects.
So anyone who is interested is hereby invited to take a look at my website. I created a forum system there and if you like to join, feel free to send me an email and I will create a login for you so you can post subjects and reply to threads.
You can find my website in the repository link URL or via https://www.knaapic.nl
The menu "Historic computing" contains dedicated pages for the repository projects.
A lot of information is the same as here but some details have been elaborated on my website.
The forum link is:
https://knaapic.nl/community/
Thank you for your interest, I look forward to hearing from you!
Kind regards,
Rodney
Updated last on july 11th, 2026.