RISC-V: Do not use vsetivli for THeadVector.

[pz9115]

in emit_vlmax_insn_lra we use a vsetivli for an immediate AVL. XTHeadVector does not support this, so guard appropriately.

Regtested on rv64gcv_zvl512b.

Regards
Robin

PR target/120461

gcc/ChangeLog:

* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Do not emit vsetivli for XTHeadVector.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/pr120461.c: New test.

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Summary by Sourcery

Guard use of immediate-AVL vsetivli in RISC-V VL-max emission so it is not used for XTHeadVector targets and add a regression test for the reported issue.

Bug Fixes:

• Avoid emitting vsetivli with immediate AVL for XTHeadVector RISC-V targets, which do not support this instruction form.

Tests:

• Add a RISC-V RVV XTHeadVector test to verify compilation with immediate AVL handling and zeroing of call-used registers.

[sourcery-ai]

Reviewer's guide (collapsed on small PRs)

Reviewer's Guide

This PR updates the RISC-V vector code generator to avoid emitting vsetivli for XTHeadVector targets when computing VLMAX in post-RA, and adds a regression test to ensure compilation succeeds for xt-c920 with specific RVV and register-zeroing options.

Flow diagram for emit_vlmax_insn_lra vsetivli emission guard

flowchart TD
  A[emit_vlmax_insn_lra] --> B["Check imm_avl_p(mode)"]
  B -->|false| E[Skip vsetivli emission]
  B -->|true| C[Check TARGET_XTHEADVECTOR]
  C -->|true| E
  C -->|false| D[Emit vsetivli for immediate AVL]
  D --> F[Continue with VLMAX handling]
  E --> F

Loading

File-Level Changes

Change	Details	Files
Guard immediate-AVL vsetivli emission in emit_vlmax_insn_lra so it is skipped for XTHeadVector targets.	Tighten the condition that checks for immediate AVL so it additionally verifies that XTHeadVector is not the active target. Preserve existing post-RA optimization comment and behavior for non-XTHeadVector targets while avoiding generation of unsupported vsetivli instructions on XTHeadVector.	gcc/config/riscv/riscv-v.cc
Add a regression test for PR target/120461 to validate code generation for XTHeadVector with RVV and zero-call-used-regs options.	Introduce a new RISC-V RVV xtheadvector test that compiles an empty function with -mcpu=xt-c920, -mrvv-vector-bits=zvl, and -fzero-call-used-regs=all. Use dg-do compile and dg-options directives to ensure the test focuses on successful compilation rather than runtime behavior.	gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c

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