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    97 repositories

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •998•2•0•0•Updated Aug 11, 2026Aug 11, 2026

    • riscv-arch-test

      Public
      Assembly
      •
      Apache License 2.0
      •346•0•0•4•Updated Aug 11, 2026Aug 11, 2026

    • isla-testgen

      Public
      ISA automatic test generator using the isla symbolic execution tool
      Rust
      •
      Other
      •5•0•0•2•Updated Aug 10, 2026Aug 10, 2026

    • sail-riscv-testgen

      Public
      Sail RISC-V model
      Sail
      •
      Other
      •287•0•0•2•Updated Aug 10, 2026Aug 10, 2026

    • CHIron

      Public
      Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
      C++
      •
      Apache License 2.0
      •5•1•0•0•Updated Aug 5, 2026Aug 5, 2026

    • riscv-dbg-vip

      Public
      Python
      •
      Apache License 2.0
      •0•0•70•1•Updated Jul 28, 2026Jul 28, 2026

    • iree-rise

      Public
      A retargetable MLIR-based machine learning compiler and runtime toolkit.
      C++
      •
      Apache License 2.0
      •979•0•0•1•Updated Jul 24, 2026Jul 24, 2026

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      SystemVerilog
      •
      Other
      •97•0•0•3•Updated Jul 24, 2026Jul 24, 2026

    • isla

      Public
      Symbolic execution tool for Sail ISA specifications
      Rust
      •
      Other
      •23•0•0•1•Updated Jul 16, 2026Jul 16, 2026

    • CVA6-fork

      Public
      The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of bo…
      Assembly
      •
      Other
      •998•0•0•0•Updated Jul 15, 2026Jul 15, 2026

    • ibex-demo-system

      Public
      A demo system for Ibex including debug support and some peripherals
      C
      •
      Apache License 2.0
      •84•0•0•0•Updated Jul 15, 2026Jul 15, 2026

    • QuantX-Hardware-Aware-Quantization

      Public
      QuantX helps AI hardware teams evaluate MXFP, BFP, NVFP, and custom quantization formats against real LLM and VLM workloads. Make data-driven numeric format dec…
      0•0•0•0•Updated Jun 24, 2026Jun 24, 2026

    • RISE-RFP-Llama.cpp

      Public
      0•1•0•0•Updated Jun 15, 2026Jun 15, 2026

    • infinite-isp_gpu

      Public
      Proprietary commercial-grade CUDA-accelerated ISP purpose-built for NVIDIA® Jetson™ edge devices and discrete GPU platforms.
      0•0•0•0•Updated Jun 10, 2026Jun 10, 2026

    • luma-iq-tool

      Public
      Premium integrated IQ analysis workbench for ISP tuning, YAML-native pipeline editing, and automated image quality evaluation
      0•0•0•0•Updated Jun 10, 2026Jun 10, 2026

    • qemu

      Public
      QEMU v11.0.1 + EDU/RISC-V IOMMU PASID, ATS/PRI & translated-request support (IOMMU transaction generator)
      C
      •
      Other
      •0•0•0•0•Updated Jun 9, 2026Jun 9, 2026

    • edu-iommu-qemu-patch

      Public
      EDU + RISC-V IOMMU PASID/ATS/PRI/translated-request patch for QEMU v11.0.1 (IOMMU transaction generator)
      GNU General Public License v2.0
      •0•0•0•0•Updated Jun 9, 2026Jun 9, 2026

    • Infinite-ISP

      Public
      A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.
      computer-visionimage-processingisp
      computer-visionimage-processingispimage-signal-processorcamera-pipeline
      Python
      •
      Apache License 2.0
      •97•367•15•0•Updated Jun 8, 2026Jun 8, 2026

    • et-soc1-docs

      Public
      ET-SoC1 Manuals and Documentation in Markdown.
      0•1•0•0•Updated May 28, 2026May 28, 2026

    • rise-yolo-iree

      Public
      C++
      •0•2•0•0•Updated May 18, 2026May 18, 2026

    • MLIR

      Public
      MLIR Tutorial
      C++
      •2•2•0•0•Updated Apr 22, 2026Apr 22, 2026

    • llvm-project-rise

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
      LLVM
      •
      Other
      •18k•0•0•0•Updated Apr 21, 2026Apr 21, 2026

    • cuda_conditional_compilation

      Public
      C++
      •0•0•0•0•Updated Apr 20, 2026Apr 20, 2026

    • llama.cpp-validation

      Public
      C++
      •1•1•0•0•Updated Apr 15, 2026Apr 15, 2026

    • github_ultraembedded_riscv_soc

      Public
      Basic RISC-V Test SoC
      Verilog
      •40•0•0•0•Updated Mar 17, 2026Mar 17, 2026

    • riscv-ci-partners

      Public
      RISC-V CI Partners Project
      HTML
      •
      MIT License
      •0•3•0•0•Updated Mar 11, 2026Mar 11, 2026

    • cudaISP_course_EI_2026

      Public
      C
      •0•0•0•0•Updated Mar 2, 2026Mar 2, 2026

    • qemu-docs

      Public
      QEMU Documentation and Tasks.
      0•0•0•0•Updated Jan 30, 2026Jan 30, 2026

    • verilator-uvm-apbuart

      Public
      APB UART verification example using a Verilator-compliant UVM testbench
      SystemVerilog
      •2•0•0•0•Updated Jan 6, 2026Jan 6, 2026

    • iopmp-spec

      Public
      This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output …
      C
      •
      Creative Commons Attribution 4.0 International
      •10•1•0•0•Updated Dec 18, 2025Dec 18, 2025
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