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Ibex single_step: dm_ref_model has no model for autonomous dcsr.step re-halt (MODEL_MISMATCH, stimulus passes)
DVVerification environment / testbench / stimulus issue, not an RTL defectVerification environment / testbench / stimulus issue, not an RTL defectStatus: Open.#132 In 10x-Engineers/riscv-dbg-vip;dmstatus.allrunning/anyrunning=1 for a nonexistent hart selection (spec violation, both DUTs)
bugSomething isn't workingSomething isn't workingRTLSuspected or confirmed RTL defect (DUT), not a DV/testbench issueSuspected or confirmed RTL defect (DUT), not a DV/testbench issueStatus: Open.#130 In 10x-Engineers/riscv-dbg-vip;CVA6: hart re-halts internally after single-step, but DM never observes it (dmstatus.allhalted stuck at 0)
bugSomething isn't workingSomething isn't workingRTLSuspected or confirmed RTL defect (DUT), not a DV/testbench issueSuspected or confirmed RTL defect (DUT), not a DV/testbench issueStatus: Open.#127 In 10x-Engineers/riscv-dbg-vip;dm_ref_model can't track a hart's autonomous self-halt (single-step) — dmstatus running/halted mismatch
bugSomething isn't workingSomething isn't workingDVVerification environment / testbench / stimulus issue, not an RTL defectVerification environment / testbench / stimulus issue, not an RTL defectStatus: Open.#119 In 10x-Engineers/riscv-dbg-vip;dm_ref_model defaults (version=0.13, impebreak=0) don't match CVA6's v1.0 fork RTL
bugSomething isn't workingSomething isn't workingDVVerification environment / testbench / stimulus issue, not an RTL defectVerification environment / testbench / stimulus issue, not an RTL defectStatus: Open.#117 In 10x-Engineers/riscv-dbg-vip; ·Milestone 13 -- External Debug features verified on simulation, 100% functional coverageSet up aggregate functional-coverage UCDB merge across Ibex scenario runs
DVVerification environment / testbench / stimulus issue, not an RTL defectVerification environment / testbench / stimulus issue, not an RTL defectStatus: Open.#112 In 10x-Engineers/riscv-dbg-vip;CVA6 v1.0 fork: abstractcs.busy stuck at 1 forever during Access Register (GPR/CSR) read, after get_response() fix
bugSomething isn't workingSomething isn't workingRTLSuspected or confirmed RTL defect (DUT), not a DV/testbench issueSuspected or confirmed RTL defect (DUT), not a DV/testbench issueStatus: Open.#104 In 10x-Engineers/riscv-dbg-vip; ·Milestone 13 -- External Debug features verified on simulation, 100% functional coverage- Status: Open.
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