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[rtl] Fix prim_generic mapping in ibex_top #2443

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Merged
SamuelRiedel merged 2 commits into from
Jun 3, 2026
+11 −2
Merged

[rtl] Fix prim_generic mapping in ibex_top #2443

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1d8e5c8
[rtl] Fix prim_generic mapping in ibex_top
SamuelRiedel Jun 1, 2026
4cd7bfd
[rtl] Explicitly define mapping to `prim_generic` for linter targets
SamuelRiedel Jun 1, 2026
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10 changes: 8 additions & 2 deletions ibex_top.core
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,6 @@ filesets:
- lowrisc:prim:onehot_check
- lowrisc:prim:onehot
- lowrisc:prim:util
- "fileset_partner ? (partner:prim_generic:all)"
- "!fileset_partner ? (lowrisc:prim_generic:all)"
files:
- rtl/ibex_register_file_ff.sv # generic FF-based
- rtl/ibex_register_file_fpga.sv # FPGA
Expand All @@ -29,6 +27,11 @@ filesets:
- rtl/ibex_top.sv
file_type: systemVerilogSource

# Map the prims listed above to the prim_generic implementations for linting
files_map_prim_generic:
depend:
- lowrisc:prim_generic:all

files_lint_verilator:
files:
- lint/verilator_waiver.vlt: {file_type: vlt}
Expand Down Expand Up @@ -163,13 +166,16 @@ targets:
default: &default_target
filesets:
- tool_verilator ? (files_lint_verilator)
- tool_verilator ? (files_map_prim_generic)
- files_rtl
- files_check_tool_requirements
toplevel: ibex_top
parameters:
- tool_vivado ? (FPGA_XILINX=true)
lint:
<<: *default_target
filesets:
- files_map_prim_generic
parameters:
- SYNTHESIS=true
- RVFI=true
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3 changes: 3 additions & 0 deletions ibex_top_tracing.core
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,9 @@ filesets:
depend:
- lowrisc:ibex:ibex_top
- lowrisc:ibex:ibex_tracer
# Map the prims in ibex_top to prim_generic implementations for simulation and linting
- "fileset_partner ? (partner:prim_generic:all)"
- "!fileset_partner ? (lowrisc:prim_generic:all)"
files:
- rtl/ibex_top_tracing.sv
file_type: systemVerilogSource
Expand Down
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