Full Custom IC Design Labs

This repository contains a series of hands-on labs designed to introduce the flow of the Full Custom IC design cycle using the Tanner EDA CAD tool. Each lab focuses on a specific aspect of IC design, from transistor characterization to layout setup.

Lab 1: Introduction to the flow of the Full Custom IC design cycle

This lab serves as a general introductory tutorial to the Full Custom IC design cycle flow.

Lab 2: CMOS Inverter Design Schematic

The objective of this lab is to characterize the NMOS & PMOS transistors by examining the “DC Sweep Analysis” and exploring the IV behavior Simulation of NMOS & PMOS transistors.

• PMOS schematic:

  

• PMOS IV Characteristics:

  

Lab 3: MOS Transistor Characterization

In this experiment, We introduce the schematic design, symbol generation, and testbench creation of the CMOS inverter. We also verify inverter functionality using Transient Analysis and characterize the CMOS inverter by examining the “DC Sweep Analysis”.

• CMOS Buffer:

  

• CMOS NAND:

  

Lab 4: CMOS Inverter chain (Ring Oscillator) Design Schematic

The Objective of this lab is to combine the CMOS inverter to build and simulate the Ring Oscillator. Students will also verify the Ring Oscillator functionality using Transient Analysis and understand the Frequency-Capacitance relationship. Capacitance tuning to generate frequencies like Digital & RF frequency will also be discussed.

• Ring Oscillator:

  

• Ring Oscillator After Smoothing the output:

  

Lab 5: Inverter Layout Setup

The objective of this lab is to build the layout for the inverter. We Place and Route (PnR) the CMOS Transistors to get the layout for the CMOS inverter and perform a Design Rules Check (DRC). We explore Layout vs Schematic (LVS) to verify layout and do Parasitic Extraction.

• Layout of CMOS:

  

• DRC:

  

• LVS:

  

Lab 6: Adder Design Schematic

In this lab, We introduce the design of combinational Logic Circuits. We explore the Half Adder design and symbol generation. Full Adder design from the Half Adder symbol will be made. We also use bit stream generation to verify the addition operation.

• Half Adder:

  • Schematic:

• Full Adder:

  • Schematic:

Lab 7: Adder Layout Setup

The objective of this lab is to build the layout of the 2-input NAND gate. Students will make Place and Route (PnR) for Adders and perform Design Rules Check (DRC). They will use Layout vs Schematic (LVS) to verify layout and do Parasitic Extraction.

• Half Adder:

  • Schematic:

  • Layout:

  • DRC:

  • LVS:

  • pEX:

• Full Adder:

  • Schematic:

  • Layout:
    

  • DRC:

  • LVS:
    

  • pEX:

Lab 8: D Latch Design

In this lab, we simulate the D latch. We design Sequential Logic Circuits. We explore the D Latch design and symbol generation. We also design a Flip Flop from the D Latch symbol and do Bitstream generation to verify functionality.

• Schematic:

  

• TestBench:

  

• Layout:

  

• DRC:

  

• LVS:

  

Getting Started

1. Clone the repository to your local machine.
2. Open each lab folder and follow the instructions provided in the README or accompanying documentation.
3. Use the Tanner EDA CAD tool to perform simulations, layout designs, and verification as instructed in each lab.

License

This project is licensed under the MIT License. Feel free to use and modify the labs for educational purposes.

Contributors

Karim Mahmoud

Aya Ahmed