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S3: Allow using non-DCache RAM#5860

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MabezDev merged 4 commits into
esp-rs:mainfrom
bugadani:dcache-ram
Jul 10, 2026
Merged

S3: Allow using non-DCache RAM#5860
MabezDev merged 4 commits into
esp-rs:mainfrom
bugadani:dcache-ram

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@bugadani

@bugadani bugadani commented Jul 9, 2026

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Closes #4069

Changelog

esp-hal

  • Removed: ESP32-S3: Removed the 16kB data cache size option
  • Added: #[ram(unstable(dcache_reclaimed))] to allow using memory not taken up by data cache

esp-hal-procmacros

  • Added: #[ram(unstable(dcache_reclaimed))] to allow using memory not taken up by data cache

Comment thread esp-hal/ld/esp32/memory.x
*/

INCLUDE "memory_extras.x"
/* reserved at the start of DRAM for the BT stack */

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👍

Comment thread esp-hal-procmacros/Cargo.toml Outdated
@bjoernQ

bjoernQ commented Jul 9, 2026

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can't comment there but in the proc-macro - shouldn't we treat the new section like dram2_uninit for the trait_check?

@bugadani

bugadani commented Jul 9, 2026

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We'll have to dig into hardware defaults - if on powerup the cache is set to 32k, we can even allow persistent data in that section. If it's 64, we can't allow initialized data, either.

Hardware default is 32K but the bootloader configures it, too, to a value set in build time 🤔

OK because the bootloader isn't under our control, we have to play this safe.

@bugadani bugadani added this pull request to the merge queue Jul 10, 2026
@github-merge-queue github-merge-queue Bot removed this pull request from the merge queue due to failed status checks Jul 10, 2026
@MabezDev MabezDev added this pull request to the merge queue Jul 10, 2026
Merged via the queue into esp-rs:main with commit 5506ab3 Jul 10, 2026
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@bugadani bugadani deleted the dcache-ram branch July 10, 2026 10:39
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Expose more RAM when smaller cache line configurations are chosen

3 participants