Create and use a new cacheline-aligned reference type#5744
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I know it's a draft but I couldn't look away from such big DMA changes....
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Overall LGTM but I'll say the InternalMemory name is still really unfortunate
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/hil full |
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Triggered full HIL run for #5744. Run: https://github.com/esp-rs/esp-hal/actions/runs/27691042282 Status update: HIL (full) run is still in progress or status unknown. |
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Not sure why the bot struggled here, HIL failed at the build stage, the tests need updating I think. |
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It's doing what I ask of it, I'm babysitting the process. |
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The goal of this PR is to make the *DmaBuf types take the cacheline-wrapped descriptors/buffers by default, and allow a safe validating, as well as an unsafe fallback option to construct them.
The new reference type has safe cache operations and can represent data living in both internal RAM and PSRAM.
This reference type will be the base of most of our DMA internals - it validates slices/descriptor lists, it can safely implement cache operations because of its invariants, and hopefully will allow us to have higher perf by avoiding unnecessary writebacks as well. It makes constructing buffers a bit less friendly, but that's hidden from us by the macros currently.
This would have been part of #5728 but it's annoyingly big by itself.
Changelog
esp-hal/DMA
esp_hal::dma::aligned::{InternalMemory, DmaAlignedMut}types.DmaAlignedMut-wrapped descriptor lists and buffers.