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1. riscv-npu-soc riscv-npu-soc Public

   A complete RISC-V SoC in SystemVerilog: pipelined CPU + memory-mapped systolic-array NPU accelerator, running real firmware that offloads a matrix multiply. Includes a small RV32I assembler. Self-c…

   SystemVerilog 1

2. apex-safety-fsm apex-safety-fsm Public

   RTL safety supervisor (SystemVerilog): an emergency-stop preempts the on-chip AI from any state and latches until a human clears it. From my APEX FPGA autonomous-vehicle SoC (SJSU EE277). Self-chec…

   SystemVerilog

3. fpga-qos-scheduler fpga-qos-scheduler Public

   Parameterized fixed-priority, non-preemptive task scheduler in SystemVerilog with a hardware safety-deadline monitor. Self-checking testbench + CI. RTL counterpart to my APEX FPGA SoC.

   SystemVerilog

4. efedemi efedemi Public

   Profile README

5. uart-core uart-core Public

   Parameterized 8N1 UART (TX + RX, oversampled) in SystemVerilog with a TX->RX loopback self-checking testbench + CI.

   SystemVerilog

6. mac-accelerator mac-accelerator Public

   Streaming signed multiply-accumulate / dot-product engine in SystemVerilog (the compute core of TinyML/NPUs). Self-checking testbench + CI.

   SystemVerilog