APB4 & AXI4 UVM Verification Portfolio

Public, non-confidential overview of my verification methodology for AMBA APB4 and AXI4 designs.

This repository intentionally contains no proprietary RTL, internal verification IP, customer material, waveform, log, or document from an internship project. It documents verification thinking, reusable structure, scenario planning, assertions, and coverage strategy.

Verification scope

Area	APB4	AXI4
Transfer flow	Setup and access phases	Independent address, data, and response channels
Handshake	PSEL, PENABLE, PREADY	VALID / READY on AW, W, B, AR, R
Response	PSLVERR	BRESP, RRESP
Attributes	PSTRB, PPROT	burst, len, size, ID, address alignment
Corner cases	wait states, back-to-back access, error response	burst types, boundary, ordering, backpressure, response errors

UVM environment structure

test
└── env
    ├── master_agent
    │   ├── sequencer
    │   ├── driver
    │   └── monitor
    ├── slave_agent_or_vip
    ├── scoreboard
    ├── coverage_collector
    └── virtual_sequencer

The environment separates stimulus generation, signal-level driving, observation, checking, and coverage collection. This keeps protocol behavior reusable across directed, constrained-random, corner, and error tests.

Scenario matrix

APB4

Group	Representative scenarios
Basic	Single read, single write, back-to-back transfers
Wait states	Delayed PREADY, variable wait length
Byte lanes	Valid and corner PSTRB patterns
Protection	PPROT combinations
Error handling	PSLVERR on read and write
Reset	Reset during idle and around active traffic

AXI4

Group	Representative scenarios
Channels	Independent AW, W, B, AR, R handshake timing
Bursts	FIXED, INCR, WRAP; legal LEN and SIZE combinations
Backpressure	Delayed READY, delayed VALID, response throttling
Addressing	Alignment and boundary-oriented scenarios
Responses	Normal and error responses
Ordering	Transaction ordering and channel relationship checks

Assertion checklist

Representative SVA targets:

• APB4 setup-to-access phase progression.
• Stable APB4 control signals while waiting for PREADY.
• Legal APB4 error timing.
• AXI4 VALID stability until handshake.
• AXI4 response channel correctness.
• Burst-related address and control consistency.
• Reset behavior and recovery.

Scoreboard strategy

sequence item
   -> driver
   -> DUT protocol interface
   -> monitor
   -> normalized transaction
   -> reference model / expected queue
   -> scoreboard comparison

The scoreboard compares transaction intent with observed behavior and reports mismatches with enough context for waveform debug.

Coverage strategy

functional coverage
  + assertion coverage
  + code coverage
  + regression analysis
  = coverage closure loop

Coverage planning includes:

• Operation type bins.
• Response bins.
• Attribute bins.
• Burst type, length, and size bins.
• Boundary and alignment cases.
• Cross coverage for meaningful combinations.
• Assertion hit and failure review.

Debug workflow

1. Reproduce the failure with a stable seed.
2. Identify the first protocol divergence.
3. Correlate scoreboard output, assertion failure, and waveform.
4. Reduce the failing scenario if necessary.
5. Fix or report the root cause.
6. Re-run targeted tests and regression.
7. Review functional, code, and assertion coverage.

Related RTL/FPGA project

For an end-to-end example combining RTL development and verification, see:

RISC-V 5-stage Pipeline with AES Accelerator on FPGA

That project includes:

• RISC-V pipeline mechanisms.
• AES accelerator over MMIO.
• Unit tests and ISA regression.
• CPU-AES end-to-end testing.
• UVM AES and CPU integration verification.
• QuestaSim waveform debug.
• Quartus FPGA deployment.

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SystemVerilog | UVM | SVA | APB4 | AXI4 | Constrained Random | Coverage | Debug