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1. FPGA_CW_6sem FPGA_CW_6sem Public

   FPGA coursework project on Verilog with GitHub workflow

   Verilog 7 1

2. Dual_Clock_FIFO Dual_Clock_FIFO Public

   Asynchronous FIFO

   Verilog 1

3. UART_Controller UART_Controller Public

   Parametrizable UART controller in Verilog with AXI-Stream interface, configurable baud rate, oversampling ratio, parity mode, stop bits, and regression testbench for verification.

   Verilog 1

4. AES_System_Model AES_System_Model Public

   AES software model in C supporting AES-128, AES-192 and AES-256 encryption and decryption with automated CTest verification.

   C 1

5. Vivado_TCL_Tools Vivado_TCL_Tools Public

   Collection of Tcl scripts for Vivado FPGA workflow automation

   Tcl 1

6. YADRO-Multi-Clock YADRO-Multi-Clock Public

   Multi clock embedded system for MIK32

   C 1