ElectroCardioGram FIR Filter in HDL

Requirements

• GHDL for VHDL simulation.
• Icarus Verilog for Verilog simulation.
• Surfer for waveform visualization.
• VHDL Style Guide for VHDL linting and formatting.
• Verible for Verilog linting and formatting.

Usage

Clone the repository

First clone the repository and navigate into it:

git clone https://github.com/AntonioBerna/ecg-fir-hdl.git
cd ecg-fir-hdl

FIR Filter Design using MATLAB

You can run the MATLAB script using MATLAB Online or locally if you have MATLAB installed. The script generates the FIR filter coefficients (impulse response) reported below:

-1, -1, 1, 13, 32, 41, 32, 13, 1, -1, -1

Note

The MATLAB script describe all the steps to design the FIR filter, including the choice of the window function and the cutoff frequencies, plotting the impulse response and the frequency response of the filter, and finally generating the coefficients. You can modify the script to design different FIR filters by changing the parameters such as the filter order, cutoff frequencies, and window type. The generated coefficients are used in both the VHDL and Verilog implementations of the FIR filter.

FIR Filter Design with Transposed Form in C

After generating the coefficients, you can run the C program to implement the FIR filter using the transposed form. The program reads the input ECG signal from a file, applies the FIR filter, and writes the filtered ECG signal to another file.

# Compile the C program
make fir

# Run the FIR filter
make fir-run

# Clean generated files
make clean

FIR Filter Design in VHDL and Verilog

# Run the HDL design and simulation
make vhdl-run
make verilog-run

# View the generated waveform
make vhdl-surfer
make verilog-surfer

# Clean generated files
make clean

Extra commands

Following commands are available to generate all the outputs at once, including the paper PDF, and to clean generated files.

# Generate all-in-one: C, HDL and paper
make

# Format and lint the HDL code
make format-vhdl
make format-verilog
make format # Both VHDL and Verilog

# Generate the paper PDF
make paper

# Clean generated PDF
make clean-pdf