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AhmedNour26/README.md

Hi there, I'm Ahmed Nour 👋

Digital IC Design & Embedded Systems Engineer

🚀 About Me

I am a passionate Hardware Engineer focused on RTL Design and Embedded Systems. I enjoy bridging the gap between hardware architecture and low-level software implementation. My portfolio includes extensive work in Verilog for IC design and bare-metal firmware for different microcontrollers.

  • 🔭 Currently working on: Advanced RTL modules and UVM verification.
  • ⚡ Key Expertise: Digital IC Design (Verilog/SystemVerilog), RTL Synthesis, and Embedded development.
  • 🌱 Learning: Analog IC designing and Advanced FPGA Architectures.

🛠️ Tech Stack & Tools

Digital Design & Hardware Verilog SystemVerilog FPGA Digital_IC

Embedded & Software C C++ STM32 Python

Tools Git VSCode ModelSim

📂 Featured Projects

🛠️ Digital IC & FPGA Design

🤖 Embedded Systems & IoT

📝 Signal Processing

Pinned Loading

  1. digital-IC-design-portfolio digital-IC-design-portfolio Public

    A centralized repository of Verilog RTL designs. Includes 50+ modules ranging from basic gates to complex FSMs, sequencers, and arithmetic circuits.

    Verilog

  2. SmartAQM_BareMetal_STM32 SmartAQM_BareMetal_STM32 Public

    This project is a high-precision environmental acquisition platform built on the ARM Cortex-M3 (STM32F103) architecture. The system provides real-time quantification of indoor air pollutants using …

    Makefile

  3. spi-slave-single-port-ram spi-slave-single-port-ram Public

    Verilog RTL design of SPI Slave with Single-Port RAM. FSM with multiple encodings, QuestaSim simulation, Vivado synthesis/implementation, debug core, and bitstream generation.

    Verilog

  4. Five-Operation-ALU_LTspice_Verilog Five-Operation-ALU_LTspice_Verilog Public

    A comprehensive ALU design project covering the full design cycle: from transistor-level schematic & simulation in LTspice to RTL modeling in Verilog.

    Verilog

  5. spartan6-dsp48a1-design spartan6-dsp48a1-design Public

    FPGA DSP project: Spartan-6 DSP48A1 slice implemented in Verilog with directed testbenches. Includes QuestaSim simulation (DO file), Vivado elaboration/synthesis/implementation, timing/utilization/…

    Verilog