-
Notifications
You must be signed in to change notification settings - Fork 2
Expand file tree
/
Copy pathrom_tb.sv.bak
More file actions
92 lines (79 loc) · 2.01 KB
/
Copy pathrom_tb.sv.bak
File metadata and controls
92 lines (79 loc) · 2.01 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
//-----------------------------------------------------------------------------
//
// Title : ROM module Testbench
// Author : vinod sake <vinosake@pdx.edu>
// Company : Student
//
//-----------------------------------------------------------------------------
//
// File : rom_tb.sv
// Generated : 25 Dec 2016
// Last Updated: 26 Dec 2016
//-----------------------------------------------------------------------------
//
// Description : performing read operations in ROM
//
//
//-----------------------------------------------------------------------------
`include "rom.sv"
parameter temp_rom_size = 1 << 4;
module rom_tb();
logic wr_en = 1'b0; // Active high
logic rd_en = 1'b0; // Active high
logic rom_enable = 1'b1; // Active low
logic [address_width-1:0]address_bus;
wire [data_width-1:0]data_bus;
integer in;
integer read;
integer write;
integer write_databus;
logic [data_width-1:0]temp_rom[rom_size-1:0];
logic [data_width-1:0]temp_rom_test[rom_size-1:0];
logic [data_width-1:0]temp_data;
logic data_control = 1'b0;
logic clock = 1'b0;
always #50 clock = ~clock;
rom rom_dut(
.wr_en(wr_en),
.rd_en(rd_en),
.rom_enable(rom_enable),
.address_bus(address_bus),
.data_bus(data_bus)
);
initial begin
//Writing into ROM
write = $fopen("write_rom.txt","r");
while(!$feof(write)) begin
@(posedge clock) begin
wr_en = 1;
rd_en = 0;
rom_enable = 0;
data_control = 1;
write_databus = $fscanf(write, "%h %h\n", address_bus,temp_data);
end
end
//Reading from ROM
read = $fopen("read_rom.txt","w");
for(int i=0; i<temp_rom_size; i=i+1) begin
@(posedge clock) begin
rd_en = 1;
wr_en = 0;
rom_enable = 0;
address_bus = i;
data_control = 0;
end
@(negedge clock) begin
$fwrite(read,"address:%h Data:%h\n", address_bus,data_bus);
end
end
$fclose(read);
$fclose(write);
$finish;
end
assign data_bus = data_control ? temp_data : 8'hzz;
// Waveform log file and monitoring
initial begin
$dumpfile("ram.vcd");
$dumpvars();
end
endmodule