name RP2 FIFO and flash-safe states

Author: rdon

src/runtime/runtime_rp2.go

@@ -13,6 +13,11 @@ import (
 	"unsafe"
 )
 
+const (
+	rp2SIOFIFOCommandGC uint32 = iota + 1
+	rp2SIOFIFOCommandFlashSafe
+)
+
 const numCPU = 2
 const numSpinlocks = 32
 
@@ -142,9 +147,9 @@ func startSecondaryCores() {
 	// second core.
 	intr := interrupt.New(sioIrqFifoProc0, func(intr interrupt.Interrupt) {
 		switch rp.SIO.FIFO_RD.Get() {
-		case 1:
+		case rp2SIOFIFOCommandGC:
 			gcInterruptHandler(0)
-		case 2:
+		case rp2SIOFIFOCommandFlashSafe:
 			rp2FlashSafeInterruptHandler(0)
 		}
 	})
@@ -178,9 +183,9 @@ func runCore1() {
 	// interrupts can still happen while the GC is running.
 	intr := interrupt.New(sioIrqFifoProc1, func(intr interrupt.Interrupt) {
 		switch rp.SIO.FIFO_RD.Get() {
-		case 1:
+		case rp2SIOFIFOCommandGC:
 			gcInterruptHandler(1)
-		case 2:
+		case rp2SIOFIFOCommandFlashSafe:
 			rp2FlashSafeInterruptHandler(1)
 		}
 	})
@@ -269,7 +274,7 @@ func gcInterruptHandler(hartID uint32) {
 
 // Pause the given core by sending it an interrupt.
 func gcPauseCore(core uint32) {
-	rp.SIO.FIFO_WR.Set(1)
+	rp.SIO.FIFO_WR.Set(rp2SIOFIFOCommandGC)
 }
 
 // Signal the given core that it can resume one step.

src/runtime/runtime_rp2040_flashsafe_cores.go

@@ -11,11 +11,9 @@ import (
 )
 
 const (
-	rp2040FlashSafeFIFOCommand = 2
-
-	rp2040FlashSafeIdle    = 0
-	rp2040FlashSafeLocked  = 1
-	rp2040FlashSafeRelease = 2
+	rp2040FlashSafeIdle uint8 = iota
+	rp2040FlashSafeLocked
+	rp2040FlashSafeRelease
 )
 
 // rp2040FlashSafeState is used to synchronize the core that performs a flash
@@ -79,7 +77,7 @@ func rp2040ExitFlashSafeSection(state interrupt.State) {
 
 func rp2040FlashSafePauseCore(core uint32) {
 	_ = core // RP2040 SIO FIFO writes to the other core.
-	rp.SIO.FIFO_WR.Set(rp2040FlashSafeFIFOCommand)
+	rp.SIO.FIFO_WR.Set(rp2SIOFIFOCommandFlashSafe)
 	arm.Asm("sev")
 }