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| 1 | +package sx128x |
| 2 | + |
| 3 | +const ( |
| 4 | + // SX128X physical layer properties |
| 5 | + FREQUENCY_STEP_SIZE = uint8(198) |
| 6 | + |
| 7 | + // SX128X SPI commands |
| 8 | + CMD_NOP = uint8(0x00) |
| 9 | + |
| 10 | + CMD_SET_UART_SPEED = uint8(0x9D) |
| 11 | + CMD_GET_STATUS = uint8(0xC0) |
| 12 | + |
| 13 | + // Register Access Operations |
| 14 | + CMD_WRITE_REGISTER = uint8(0x18) |
| 15 | + CMD_READ_REGISTER = uint8(0x19) |
| 16 | + |
| 17 | + // Data Buffer Operations |
| 18 | + CMD_WRITE_BUFFER = uint8(0x1A) |
| 19 | + CMD_READ_BUFFER = uint8(0x1B) |
| 20 | + |
| 21 | + // Radio Operation Modes |
| 22 | + CMD_SET_SLEEP = uint8(0x84) |
| 23 | + CMD_SET_STANDBY = uint8(0x80) |
| 24 | + CMD_SET_FS = uint8(0xC1) |
| 25 | + CMD_SET_TX = uint8(0x83) |
| 26 | + CMD_SET_RX = uint8(0x82) |
| 27 | + CMD_SET_RX_DUTY_CYCLE = uint8(0x94) |
| 28 | + CMD_SET_LONG_PREAMBLE = uint8(0x9B) |
| 29 | + CMD_SET_CAD = uint8(0xC5) |
| 30 | + CMD_SET_TX_CONTINUOUS_WAVE = uint8(0xD1) |
| 31 | + CMD_SET_TX_CONTINUOUS_PREAMBLE = uint8(0xD2) |
| 32 | + CMD_SET_AUTO_TX = uint8(0x98) |
| 33 | + CMD_SET_AUTO_FS = uint8(0x9E) |
| 34 | + |
| 35 | + // Radio Configuration |
| 36 | + CMD_SET_PACKET_TYPE = uint8(0x8A) |
| 37 | + CMD_GET_PACKET_TYPE = uint8(0x03) |
| 38 | + CMD_SET_RF_FREQUENCY = uint8(0x86) |
| 39 | + CMD_SET_TX_PARAMS = uint8(0x8E) |
| 40 | + CMD_SET_CAD_PARAMS = uint8(0x88) |
| 41 | + CMD_SET_BUFFER_BASE_ADDRESS = uint8(0x8F) |
| 42 | + CMD_SET_MODULATION_PARAMS = uint8(0x8B) |
| 43 | + CMD_SET_PACKET_PARAMS = uint8(0x8C) |
| 44 | + |
| 45 | + // Communication Status Information |
| 46 | + CMD_GET_RX_BUFFER_STATUS = uint8(0x17) |
| 47 | + CMD_GET_PACKET_STATUS = uint8(0x1D) |
| 48 | + CMD_GET_RSSI_INST = uint8(0x1F) |
| 49 | + |
| 50 | + // IRQ Handling |
| 51 | + CMD_SET_DIO_IRQ_PARAMS = uint8(0x8D) |
| 52 | + CMD_GET_IRQ_STATUS = uint8(0x15) |
| 53 | + CMD_CLEAR_IRQ_STATUS = uint8(0x97) |
| 54 | + |
| 55 | + // Miscellaneous |
| 56 | + CMD_SET_REGULATOR_MODE = uint8(0x96) |
| 57 | + CMD_SET_SAVE_CONTEXT = uint8(0xD5) |
| 58 | + |
| 59 | + // GetStatus |
| 60 | + CIRCUIT_MODE_MASK = uint8(0b11100000) |
| 61 | + CIRCUIT_MODE_STDBY_RC = uint8(0x2) |
| 62 | + CIRCUIT_MODE_STDBY_XOSC = uint8(0x3) |
| 63 | + CIRCUIT_MODE_FS = uint8(0x4) |
| 64 | + CIRCUIT_MODE_RX = uint8(0x5) |
| 65 | + CIRCUIT_MODE_TX = uint8(0x6) |
| 66 | + |
| 67 | + COMMAND_STATUS_MASK = uint8(0b00011100) |
| 68 | + COMMAND_STATUS_SUCCESS = uint8(0x1) |
| 69 | + COMMAND_STATUS_DATA_AVAILABLE = uint8(0x2) |
| 70 | + COMMAND_STATUS_TIMEOUT = uint8(0x3) |
| 71 | + COMMAND_STATUS_PROCESSING_ERROR = uint8(0x4) |
| 72 | + COMMAND_STATUS_EXECUTION_ERROR = uint8(0x5) |
| 73 | + COMMAND_STATUS_TX_DONE = uint8(0x6) |
| 74 | + |
| 75 | + // SleepConfig |
| 76 | + SLEEP_DATA_BUFFER_RETAIN = uint8(2) |
| 77 | + SLEEP_DATA_RAM_RETAIN = uint8(1) |
| 78 | + |
| 79 | + // StandbyConfig |
| 80 | + STANDBY_RC = uint8(0) |
| 81 | + STANDBY_XOSC = uint8(1) |
| 82 | + |
| 83 | + // PeriodBase |
| 84 | + PERIOD_BASE_15_625_US = uint8(0) |
| 85 | + PERIOD_BASE_62_5_US = uint8(1) |
| 86 | + PERIOD_BASE_1_MS = uint8(2) |
| 87 | + PERIOD_BASE_4_MS = uint8(3) |
| 88 | + |
| 89 | + RX_CONTINUOUS_MODE = uint16(0xFFFF) |
| 90 | + |
| 91 | + // LongPreamble |
| 92 | + LONG_PREAMBLE_ENABLE = uint8(1) |
| 93 | + LONG_PREAMBLE_DISABLE = uint8(0) |
| 94 | + |
| 95 | + // AutoFs |
| 96 | + AUTO_FS_ENABLE = uint8(1) |
| 97 | + AUTO_FS_DISABLE = uint8(0) |
| 98 | + |
| 99 | + // PacketType |
| 100 | + PACKET_TYPE_GFSK = uint8(0x00) // default |
| 101 | + PACKET_TYPE_LORA = uint8(0x01) |
| 102 | + PACKET_TYPE_RANGING = uint8(0x02) |
| 103 | + PACKET_TYPE_FLRC = uint8(0x03) |
| 104 | + PACKET_TYPE_BLE = uint8(0x04) |
| 105 | + |
| 106 | + // RampTime |
| 107 | + RADIO_RAMP_02_US = uint8(0x00) |
| 108 | + RADIO_RAMP_04_US = uint8(0x20) |
| 109 | + RADIO_RAMP_06_US = uint8(0x40) |
| 110 | + RADIO_RAMP_08_US = uint8(0x60) |
| 111 | + RADIO_RAMP_10_US = uint8(0x80) |
| 112 | + RADIO_RAMP_12_US = uint8(0xA0) |
| 113 | + RADIO_RAMP_16_US = uint8(0xC0) |
| 114 | + RADIO_RAMP_20_US = uint8(0xE0) |
| 115 | + |
| 116 | + // CadSymbolNum |
| 117 | + LORA_CAD_01_SYMBOL = uint8(0x00) |
| 118 | + LORA_CAD_02_SYMBOLS = uint8(0x20) |
| 119 | + LORA_CAD_04_SYMBOLS = uint8(0x40) |
| 120 | + LORA_CAD_08_SYMBOLS = uint8(0x60) |
| 121 | + LORA_CAD_16_SYMBOLS = uint8(0x80) |
| 122 | + |
| 123 | + // SpreadingFactor |
| 124 | + LORA_SF_5 = uint8(0x50) |
| 125 | + LORA_SF_6 = uint8(0x60) |
| 126 | + LORA_SF_7 = uint8(0x70) |
| 127 | + LORA_SF_8 = uint8(0x80) |
| 128 | + LORA_SF_9 = uint8(0x90) |
| 129 | + LORA_SF_10 = uint8(0xA0) |
| 130 | + LORA_SF_11 = uint8(0xB0) |
| 131 | + LORA_SF_12 = uint8(0xC0) |
| 132 | + |
| 133 | + // Bandwidth |
| 134 | + LORA_BW_1600 = uint8(0x0A) |
| 135 | + LORA_BW_800 = uint8(0x18) |
| 136 | + LORA_BW_400 = uint8(0x26) |
| 137 | + LORA_BW_200 = uint8(0x34) |
| 138 | + |
| 139 | + // CodingRate |
| 140 | + LORA_CR_4_5 = uint8(0x01) |
| 141 | + LORA_CR_4_6 = uint8(0x02) |
| 142 | + LORA_CR_4_7 = uint8(0x03) |
| 143 | + LORA_CR_4_8 = uint8(0x04) |
| 144 | + LORA_CR_LI_4_5 = uint8(0x05) |
| 145 | + LORA_CR_LI_4_6 = uint8(0x06) |
| 146 | + LORA_CR_LI_4_8 = uint8(0x07) |
| 147 | + |
| 148 | + // LoraPacketParams |
| 149 | + LORA_EXPLICIT_HEADER = uint8(0x00) |
| 150 | + LORA_IMPLICIT_HEADER = uint8(0x80) |
| 151 | + |
| 152 | + LORA_CRC_ENABLE = uint8(0x20) |
| 153 | + LORA_CRC_DISABLE = uint8(0x00) |
| 154 | + |
| 155 | + LORA_IQ_INVERTED = uint8(0x00) |
| 156 | + LORA_IQ_STD = uint8(0x40) |
| 157 | + |
| 158 | + // RegulatorMode |
| 159 | + REGULATOR_LDO = uint8(0) |
| 160 | + REGULATOR_DC_DC = uint8(1) |
| 161 | + |
| 162 | + // IRQ masks |
| 163 | + IRQ_ALL_MASK = uint16(0xFFFF) |
| 164 | + IRQ_NONE_MASK = uint16(0x0000) |
| 165 | + IRQ_TX_DONE_MASK = uint16(0b0000000000000001) |
| 166 | + IRQ_RX_DONE_MASK = uint16(0b0000000000000010) |
| 167 | + IRQ_SYNC_WORD_VALID_MASK = uint16(0b0000000000000100) |
| 168 | + IRQ_SYNC_WORD_ERROR_MASK = uint16(0b0000000000001000) |
| 169 | + IRQ_HEADER_VALID_MASK = uint16(0b0000000000010000) |
| 170 | + IRQ_HEADER_ERROR_MASK = uint16(0b0000000000100000) |
| 171 | + IRQ_CRC_ERROR_MASK = uint16(0b0000000001000000) |
| 172 | + IRQ_RANGING_SLAVE_RESPONSE_DONE_MASK = uint16(0b0000000010000000) |
| 173 | + IRQ_RANGING_SLAVE_RESPONSE_DISCARD_MASK = uint16(0b0000000100000000) |
| 174 | + IRQ_RANGING_MASTER_RESULT_VALID_MASK = uint16(0b0000001000000000) |
| 175 | + IRQ_RANGING_MASTER_TIMEOUT_MASK = uint16(0b0000010000000000) |
| 176 | + IRQ_RANGING_SLAVE_REQUEST_VALID_MASK = uint16(0b0000100000000000) |
| 177 | + IRQ_CAD_DONE_MASK = uint16(0b0001000000000000) |
| 178 | + IRQ_CAD_DETECTED_MASK = uint16(0b0010000000000000) |
| 179 | + IRQ_RX_TX_TIMEOUT_MASK = uint16(0b0100000000000000) |
| 180 | + IRQ_PREAMBLE_DETECTED_MASK = uint16(0b1000000000000000) |
| 181 | + IRQ_ADVANCED_RANGING_DONE_MASK = uint16(0b1000000000000000) |
| 182 | + |
| 183 | + // SX128X register map |
| 184 | + REG_FIRMWARE_VERSIONS = uint16(0x153) |
| 185 | + REG_RX_GAIN = uint16(0x891) |
| 186 | + REG_MANUAL_GAIN_SETTING = uint16(0x895) |
| 187 | + REG_LNA_GAIN_VALUE = uint16(0x89E) |
| 188 | + REG_LNA_GAIN_CONTROL = uint16(0x89F) |
| 189 | + REG_SYNCH_PEAK_ATTENUATION = uint16(0x8C2) |
| 190 | + REG_PAYLOAD_LENGTH = uint16(0x901) |
| 191 | + REG_LORA_HEADER_MODE = uint16(0x903) |
| 192 | + REG_RANGING_REQUEST_ADDRESS_BYTE_3 = uint16(0x912) |
| 193 | + REG_RANGING_REQUEST_ADDRESS_BYTE_2 = uint16(0x913) |
| 194 | + REG_RANGING_REQUEST_ADDRESS_BYTE_1 = uint16(0x914) |
| 195 | + REG_RANGING_REQUEST_ADDRESS_BYTE_0 = uint16(0x915) |
| 196 | + REG_RANGING_DEVICE_ADDRESS_BYTE_3 = uint16(0x916) |
| 197 | + REG_RANGING_DEVICE_ADDRESS_BYTE_2 = uint16(0x917) |
| 198 | + REG_RANGING_DEVICE_ADDRESS_BYTE_1 = uint16(0x918) |
| 199 | + REG_RANGING_DEVICE_ADDRESS_BYTE_0 = uint16(0x919) |
| 200 | + REG_RANGING_FILTER_WINDOW_SIZE = uint16(0x91E) |
| 201 | + REG_RESET_RANGING_FILTER = uint16(0x923) |
| 202 | + REG_RANGING_RESULT_MUX = uint16(0x924) |
| 203 | + REG_SF_ADDITIONAL_CONFIGURATION = uint16(0x925) |
| 204 | + REG_RANGING_CALIBRATION_BYTE_2 = uint16(0x92B) |
| 205 | + REG_RANGING_CALIBRATION_BYTE_1 = uint16(0x92C) |
| 206 | + REG_RANGING_CALIBRATION_BYTE_0 = uint16(0x92D) |
| 207 | + REG_RANGING_ID_CHECK_LENGTH = uint16(0x931) |
| 208 | + REG_FREQUENCY_ERROR_CORRECTION = uint16(0x93C) |
| 209 | + REG_CAD_DETECT_PEAK = uint16(0x942) |
| 210 | + REG_LORA_SYNC_WORD_MSB = uint16(0x944) |
| 211 | + REG_LORA_SYNC_WORD_LSB = uint16(0x945) |
| 212 | + REG_HEADER_CRC = uint16(0x954) |
| 213 | + REG_CODING_RATE = uint16(0x950) |
| 214 | + REG_FEI_BYTE_2 = uint16(0x954) |
| 215 | + REG_FEI_BYTE_1 = uint16(0x955) |
| 216 | + REG_FEI_BYTE_0 = uint16(0x956) |
| 217 | + REG_RANGING_RESULT_BYTE_2 = uint16(0x961) |
| 218 | + REG_RANGING_RESULT_BYTE_1 = uint16(0x962) |
| 219 | + REG_RANGING_RESULT_BYTE_0 = uint16(0x963) |
| 220 | + REG_RANGING_RSSI = uint16(0x964) |
| 221 | + REG_FREEZE_RANGING_RESULT = uint16(0x97F) |
| 222 | + REG_PACKET_PREAMBLE_SETTINGS = uint16(0x9C1) |
| 223 | + REG_WHITENING_INITIAL_VALUE = uint16(0x9C5) |
| 224 | + REG_CRC_POLYNOMIAL_DEFINITION_MSB = uint16(0x9C6) |
| 225 | + REG_CRC_POLYNOMIAL_DEFINITION_LSB = uint16(0x9C7) |
| 226 | + REG_CRC_POLYNOMIAL_SEED_BYTE_2 = uint16(0x9C7) |
| 227 | + REG_CRC_POLYNOMIAL_SEED_BYTE_1 = uint16(0x9C8) |
| 228 | + REG_CRC_POLYNOMIAL_SEED_BYTE_0 = uint16(0x9C9) |
| 229 | + REG_CRC_MSB_INITIAL_VALUE = uint16(0x9C8) |
| 230 | + REG_CRC_LSB_INITIAL_VALUE = uint16(0x9C9) |
| 231 | + REG_SYNC_ADDRESS_CONTROL = uint16(0x9CD) |
| 232 | + REG_SYNC_ADDRESS_1_BYTE_4 = uint16(0x9CE) |
| 233 | + REG_SYNC_ADDRESS_1_BYTE_3 = uint16(0x9CF) |
| 234 | + REG_SYNC_ADDRESS_1_BYTE_2 = uint16(0x9D0) |
| 235 | + REG_SYNC_ADDRESS_1_BYTE_1 = uint16(0x9D1) |
| 236 | + REG_SYNC_ADDRESS_1_BYTE_0 = uint16(0x9D2) |
| 237 | + REG_SYNC_ADDRESS_2_BYTE_4 = uint16(0x9D3) |
| 238 | + REG_SYNC_ADDRESS_2_BYTE_3 = uint16(0x9D4) |
| 239 | + REG_SYNC_ADDRESS_2_BYTE_2 = uint16(0x9D5) |
| 240 | + REG_SYNC_ADDRESS_2_BYTE_1 = uint16(0x9D6) |
| 241 | + REG_SYNC_ADDRESS_2_BYTE_0 = uint16(0x9D7) |
| 242 | + REG_SYNC_ADDRESS_3_BYTE_4 = uint16(0x9D8) |
| 243 | + REG_SYNC_ADDRESS_3_BYTE_3 = uint16(0x9D9) |
| 244 | + REG_SYNC_ADDRESS_3_BYTE_2 = uint16(0x9DA) |
| 245 | + REG_SYNC_ADDRESS_3_BYTE_1 = uint16(0x9DB) |
| 246 | + REG_SYNC_ADDRESS_3_BYTE_0 = uint16(0x9DC) |
| 247 | +) |
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