The processor executes hexadecimal-encoded instructions fetched from data memory. These instructions are pipelined through a custom decoding unit and executed using a 16-bit carry-select adder/subtractor, which utilizes a two's complement representation to handle subtraction. The instruction set architecture supports basic control flow, including unconditional and conditional jumps, enabling loops and conditional branching.
Designed around a Harvard architecture, the processor separates instruction and data pathways, making it fully capable of executing standard sorting and searching algorithms. Additionally, the system's execution and output changes can be monitored in real time as the clock oscillates through an in-built 7 segment display.
The core architecture and project goals are credited to my Digital Electronics teacher.
NOTE: The simulator, Logism, requires Java to run. The releases of logism can be found here.