mstatus.MDT/MIE need additional behavior

[ThinkOpenly]

Per spec:

Upon reset, the MDT field is set to 1. When the MDT bit is set to 1 by an explicit CSR write, the MIE bit is cleared to 0. For RV64, this clearing occurs regardless of the value written, if any, to the MIE bit by the same write. The MIE bit can only be set to 1 by an explicit CSR write if the MDT bit is already 0 or, for RV64, is being set to 0 by the same write (For RV32, the MDT bit is in mstatush and the MIE bit in mstatus register).

Most of that will be fairly straightforward.

Difficult is "clearing [MIE] occurs regardless of the value written to the MIE bit ... by the same write".

[cavemansatyn-design]

Paul Clarke (@ThinkOpenly) !
I took a closer look at this issue and plan to split it into two small, reviewable changes:

1. First, I'll submit a PR correcting the reset_value for mstatus.MDT and mstatush.MDT from UNDEFINED_LEGAL to 1, since both the privileged spec and the existing field description already state that MDT is set to 1 on reset.
2. Then I'll follow up with a separate PR for the explicit CSR write behavior (MDT/MIE coupling), since that is a larger behavioral change and seems better reviewed independently.