From 1d8e5c8106cf9287d15522a886d5ab729973bbb5 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 1 Jun 2026 15:00:41 +0200 Subject: [PATCH 1/2] [rtl] Fix prim_generic mapping in ibex_top Explicitly include `lowrisc:prim_generic:all` in `ibex_top_tracing` instead of `ibex_top` to bind abstract `prim` dependencies to a specific implementation (generic, in this case). This is done to resolve the primitive mappings rather than to fix missing source dependencies. The dependencies are all listed as virtual `prim`s in `ibex_top`. Keeping this mapping isolated ensures that other wrappers can cleanly bind `ibex_top` to alternative backends, such as `prim_xilinx` for FPGA targets. --- ibex_top.core | 2 -- ibex_top_tracing.core | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/ibex_top.core b/ibex_top.core index 08cae5407..b772066a9 100644 --- a/ibex_top.core +++ b/ibex_top.core @@ -19,8 +19,6 @@ filesets: - lowrisc:prim:onehot_check - lowrisc:prim:onehot - lowrisc:prim:util - - "fileset_partner ? (partner:prim_generic:all)" - - "!fileset_partner ? (lowrisc:prim_generic:all)" files: - rtl/ibex_register_file_ff.sv # generic FF-based - rtl/ibex_register_file_fpga.sv # FPGA diff --git a/ibex_top_tracing.core b/ibex_top_tracing.core index 92b0f5a2e..6c7e3d11b 100644 --- a/ibex_top_tracing.core +++ b/ibex_top_tracing.core @@ -9,6 +9,9 @@ filesets: depend: - lowrisc:ibex:ibex_top - lowrisc:ibex:ibex_tracer + # Map the prims in ibex_top to prim_generic implementations for simulation and linting + - "fileset_partner ? (partner:prim_generic:all)" + - "!fileset_partner ? (lowrisc:prim_generic:all)" files: - rtl/ibex_top_tracing.sv file_type: systemVerilogSource From 4cd7bfde3bb775930717cdc49e358ee34af63823 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 1 Jun 2026 15:45:42 +0200 Subject: [PATCH 2/2] [rtl] Explicitly define mapping to `prim_generic` for linter targets Adding a dependency on a specific implementation (`prim_generic`) of the virtual `prim` core for linter and Verilator targets forces FuseSoC to use the correct instances, thereby allowing us to lint or export filelists of `ibex_top` without a wrapper defining the virtual core's implementation. --- ibex_top.core | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/ibex_top.core b/ibex_top.core index b772066a9..82edbe133 100644 --- a/ibex_top.core +++ b/ibex_top.core @@ -27,6 +27,11 @@ filesets: - rtl/ibex_top.sv file_type: systemVerilogSource + # Map the prims listed above to the prim_generic implementations for linting + files_map_prim_generic: + depend: + - lowrisc:prim_generic:all + files_lint_verilator: files: - lint/verilator_waiver.vlt: {file_type: vlt} @@ -161,6 +166,7 @@ targets: default: &default_target filesets: - tool_verilator ? (files_lint_verilator) + - tool_verilator ? (files_map_prim_generic) - files_rtl - files_check_tool_requirements toplevel: ibex_top @@ -168,6 +174,8 @@ targets: - tool_vivado ? (FPGA_XILINX=true) lint: <<: *default_target + filesets: + - files_map_prim_generic parameters: - SYNTHESIS=true - RVFI=true