diff --git a/ibex_top.core b/ibex_top.core
index 08cae5407..82edbe133 100644
--- a/ibex_top.core
+++ b/ibex_top.core
@@ -19,8 +19,6 @@ filesets:
       - lowrisc:prim:onehot_check
       - lowrisc:prim:onehot
       - lowrisc:prim:util
-      - "fileset_partner ? (partner:prim_generic:all)"
-      - "!fileset_partner ? (lowrisc:prim_generic:all)"
     files:
       - rtl/ibex_register_file_ff.sv # generic FF-based
       - rtl/ibex_register_file_fpga.sv # FPGA
@@ -29,6 +27,11 @@ filesets:
       - rtl/ibex_top.sv
     file_type: systemVerilogSource
 
+  # Map the prims listed above to the prim_generic implementations for linting
+  files_map_prim_generic:
+      depend:
+        - lowrisc:prim_generic:all
+
   files_lint_verilator:
     files:
       - lint/verilator_waiver.vlt: {file_type: vlt}
@@ -163,6 +166,7 @@ targets:
   default: &default_target
     filesets:
       - tool_verilator ? (files_lint_verilator)
+      - tool_verilator ? (files_map_prim_generic)
       - files_rtl
       - files_check_tool_requirements
     toplevel: ibex_top
@@ -170,6 +174,8 @@ targets:
       - tool_vivado ? (FPGA_XILINX=true)
   lint:
     <<: *default_target
+    filesets:
+      - files_map_prim_generic
     parameters:
       - SYNTHESIS=true
       - RVFI=true
diff --git a/ibex_top_tracing.core b/ibex_top_tracing.core
index 92b0f5a2e..6c7e3d11b 100644
--- a/ibex_top_tracing.core
+++ b/ibex_top_tracing.core
@@ -9,6 +9,9 @@ filesets:
     depend:
       - lowrisc:ibex:ibex_top
       - lowrisc:ibex:ibex_tracer
+      # Map the prims in ibex_top to prim_generic implementations for simulation and linting
+      - "fileset_partner ? (partner:prim_generic:all)"
+      - "!fileset_partner ? (lowrisc:prim_generic:all)"
     files:
       - rtl/ibex_top_tracing.sv
     file_type: systemVerilogSource