deploy: f8ea634

Author: tmichalak

.buildinfo

@@ -1,4 +1,4 @@
 # Sphinx build info version 1
 # This file records the configuration used when building these files. When it is not found, a full rebuild will be done.
-config: 63627bd573fa8d05f077ba4a9a9b417a
+config: 11337e8a4ab00341a4c66bf5e454d76e
 tags: 645f666f9bcd5a90fca523b33c5a78b7

_images/flow_active_fsm.png

@@ -12,12 +12,21 @@ The following Broadcast CCCs are currently supported by the core (all required B
 * DISEC (R) - Disable Events Command
 * SETMWL (R) - Set Max Write Length
 * SETMRL (R) - Set Max Read Length
-* SETAASA (O) - Set All Addresses to Static Adresses
+* SETAASA (O) - Set All Addresses to Static Addresses
 * ENTDAA (R) - Enter Dynamic Address Assignment
-* RSTDAA (R) - Direct Reset Dynamic Address Assignment - this direct CCC is deprecated, the core NACKs this command as per the spec
+* RSTDAA (R) - Reset Dynamic Address Assignment
 * RSTACT (R) - Target Reset Action
   * Broadcast (Format 1) supports defining bytes 0x0, 0x1 and 0x2
 
+The following Broadcast CCCs are recognized but not actively handled (the core ACKs or NACKs as appropriate per the specification):
+
+* ENTAS0-ENTAS3 - Enter Activity State (acknowledged, no behavioral change)
+* ENTHDR0-ENTHDR7 - Enter HDR Mode (triggers HDR mode entry; HDR data transfer is not supported)
+* ENDXFER - Data Transfer Ending Procedure Control
+* SETBUSCON - Set Bus Context
+* DEFGRPA / RSTGRPA - Group Address (not supported, NACKed)
+* MLANE - Multi-Lane (not supported, NACKed)
+
 ## Direct CCCs
 
 The following Direct CCCs are currently supported by the core (all required Direct CCCs, plus several optional/conditional ones):
@@ -30,14 +39,89 @@ The following Direct CCCs are currently supported by the core (all required Dire
 * SETMWL (R) - Set Max Write Length
 * SETMRL (R) - Set Max Read Length
 * GETMWL (R) - Get Max Write Length
-* GETMRL (R) - Set Max Read Length
+* GETMRL (R) - Get Max Read Length
 * GETPID (C) - Get Provisioned ID
 * GETBCR (C) - Get Bus Characteristics Register
 * GETDCR (C) - Get Device Characteristics Register
 * GETSTATUS (R) - Get Device Status
   * The two-byte format (Format 1)
 * GETCAPS (R) - Get Optional Feature Capabilities
-  * Without defining byte ( Format 1)
+  * Without defining byte (Format 1)
+  * With defining byte 0x93
 * RSTACT (R) - Target Reset Action
   * Direct Write (Format 2) supports defining bytes 0x0, 0x1 and 0x2
-  * Direct Read (Format 3) supports defining bytes 0x81 and 0x82 and returns the 0xFF as recovery timing
+  * Direct Read (Format 3) supports defining bytes 0x81, 0x82, and 0x84 and returns 0xFF as recovery timing
+* ENDXFER - Data Transfer Ending Procedure Control
+
+## CCCs That Update Registers Without Firmware Notification
+
+The following CCCs autonomously update internal registers without generating an
+interrupt to notify firmware. Firmware should poll these registers if current
+values are needed:
+
+| CCC | Register Updated | Notes |
+|-----|-----------------|-------|
+| SETDASA | `STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR` / `DYNAMIC_ADDR_VALID` | Sets dynamic address (main or virtual) |
+| SETNEWDA | `STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR` / `DYNAMIC_ADDR_VALID` | Assigns a new dynamic address (main or virtual) |
+| SETAASA | `STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR` / `DYNAMIC_ADDR_VALID` | Copies static address to dynamic address (main and/or virtual) |
+| RSTDAA | `STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR` / `DYNAMIC_ADDR_VALID` | Clears dynamic address and valid bit (main and virtual) |
+| SETMRL (Broadcast/Direct) | `STBY_CR_MRL.MRL` | Max Read Length; not enforced in hardware |
+| SETMRL (with IBI length) | `STBY_CR_MRL.IBIL` | IBI data length |
+| SETMWL (Broadcast/Direct) | `STBY_CR_MWL.MWL` | Max Write Length; not enforced in hardware |
+| RSTACT | `STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION` | Reset action level (defaults to 0x1 when no RSTACT is active) |
+| ENEC | `TTI.CONTROL.IBI_EN`, `CRR_EN`, `HJ_EN` | Enables the corresponding event |
+| DISEC | `TTI.CONTROL.IBI_EN`, `CRR_EN`, `HJ_EN` | Disables the corresponding event |
+
+```{note}
+MRL and MWL values are informational only. The hardware does not enforce these
+limits on Private Read or Private Write transfers. See {doc}`firmware_guide` for
+details on firmware responsibilities.
+```
+
+## Multi-Byte CCC Register Atomicity
+
+Several Direct GET CCCs return multi-byte values. The CCC state machine
+transmits these byte-by-byte, selecting each byte from the source signal
+combinationally as it is needed. There is no snapshot or shadow register;
+the source is re-read on every byte. If the underlying CSR is modified
+mid-transfer, remaining bytes will reflect the new value while
+already-transmitted bytes retain the old value.
+
+| CCC | Bytes | Source | Updated By |
+|-----|-------|--------|------------|
+| GETBCR | 1 | `STBY_CR_DEVICE_CHAR.BCR_*` | FW |
+| GETDCR | 1 | `STBY_CR_DEVICE_CHAR.DCR` | FW |
+| GETSTATUS | 2 | `TTI.INTERRUPT_STATUS`, `TTI.STATUS` | HW |
+| GETMWL | 2 | Internal flop | SETMWL CCC |
+| GETMRL | 3 | Internal flop | SETMRL CCC |
+| GETPID | 6 | `STBY_CR_DEVICE_CHAR.PID_HI` + `STBY_CR_DEVICE_PID_LO.PID_LO` | FW |
+
+**GETPID**: The 48-bit PID is assembled combinationally from two CSR
+registers (`STBY_CR_DEVICE_CHAR` and `STBY_CR_DEVICE_PID_LO`). If firmware
+writes either register while a GETPID CCC is in progress, the byte being
+transmitted in that cycle and all subsequent bytes will use the new register
+value. Firmware should write both PID registers before the Target receives
+a dynamic address (before ENTDAA / SETDASA / SETAASA), since GETPID is
+only issued after address assignment.
+
+**GETMWL / GETMRL**: These read internal flops that are only written by the
+SETMWL / SETMRL CCC handler. Since only one CCC can be active on the bus at
+a time, GET and SET cannot overlap. These registers are read-only to firmware
+(`sw = r`).
+
+For SET CCCs, **SETMRL** commits MRL (bytes 0-1) and IBIL (byte 2) to
+`STBY_CR_MRL` on separate clock cycles. A firmware read of `STBY_CR_MRL`
+between those two updates sees the new MRL with the stale IBIL. **SETMWL**
+commits both MWL bytes to `STBY_CR_MWL` in a single cycle.
+
+## CCC Error Handling
+
+The core detects errors during CCC processing:
+
+* **TE1**: CCC command code parity error
+* **TE5**: Wrong R/W direction for a Direct CCC (e.g., SET command with Read)
+* **Framing Error**: SETDASA/SETNEWDA padding bit error (Bit[0] != 0)
+
+These errors are reported through the `TTI.TARGET_ERR_INTR_STATUS` register
+and the `TTI.STATUS.PROTOCOL_ERROR` bit (readable via GETSTATUS CCC).
+See {doc}`error_handling` for full details.