[Support Matrix] DeepSeek-V4 support on trtllm (multiple op collectors missing: mHC done, DSV4 sparse-attention modules outstanding)

[tianhaox]

What coverage are you requesting?

Model (HuggingFace ID):
deepseek-ai/DeepSeek-V4-Flash, deepseek-ai/DeepSeek-V4-Pro, sgl-project/DeepSeek-V4-Flash-FP8, sgl-project/DeepSeek-V4-Pro-FP8

Hardware / System:
All 8 trtllm-collected systems (b200_sxm, b300_sxm, gb200, gb300, h100_sxm, h200_sxm, l40s, rtx_pro_6000_server)

Backend / Framework:
trtllm

Backend Version (if specific):
1.3.0rc20 (and future versions)

Mode

• Aggregated (agg)
• Disaggregated (disagg)
• Both

Scope (revised 2026-08-06)

This issue originally asked only for an mHC module collector — that was the first error the support matrix surfaced, not the full gap. Empirical re-check (mhc data injected locally, then re-run generate_support_matrix.py --system b200_sxm --backend trtllm): the next failure is DeepSeek-V4 context attention module data not loaded, and HYBRID mode cannot estimate either (no own-shape/cross-shape/sibling reference rows). The real scope is full DeepSeek-V4 modeling support on trtllm, which needs multiple op families, not just mHC.

Per-op status for DSV4 on trtllm 1.3.0rc20:

Op family	Collector	Data	Notes
gemm / moe / mla / comm / quantize	✅ exists	✅ collected	moe already covers both DSV4 expert geometries (4096/2048/topk6/e256, 7168/3072/topk6/e384)
mhc_module (pre/post)	✅ PR #1486	✅ collected on all 8 systems 2026-08-05 (1101 rows; publish pending)	SM89/SM120 run FMA-only, SM90/100/103 add DeepGEMM TF32 tactics — observed per row via kernel_source
dsv4 sparse-attention modules (dsv4_csa_context_module, dsv4_hca_context_module, dsv4_csa_generation_module, dsv4_hca_generation_module)	❌ missing (sglang has 8 dsv4 ops, vllm has 6, trtllm has 0)	❌ none	SDK ContextDeepSeekV4AttentionModule / GenerationDeepSeekV4AttentionModule query these tables on every backend

Remaining work

1. Author collector/trtllm/ DSV4 sparse-attention module collectors (csa/hca × context/generation) + registry entries + DSV4 plan activation. TRT-LLM 1.3.0rc20 ships the serving-side sparse backend in the wheel (tensorrt_llm/_torch/attention_backend/sparse/deepseek_v4/: backend + cache_manager + compressor) but no DeepseekV4 model class yet — same module-API situation as mHC (kernel-source-of-truth rule: drive the framework's own dispatch). Reference implementations: collector/sglang/deepseekv4_sparse_modules.py, collector/vllm dsv4 module collectors.
2. Collect the four module tables on the trtllm-covered systems (mhc campaign pipeline is reusable). Expect platform limits on SM89/SM120 analogous to the sglang side (l40s has no dsv4 data at all; rtx_pro is missing dsv4_csa_context) — handle with probe evidence, not predictions.
3. Publish mhc + dsv4 module data, regenerate the support matrix, and confirm DeepSeek-V4 agg/disagg rows pass on trtllm.

DeepSeek-V4 agg/disagg on trtllm cannot be modeled by AIC until ALL of the above land; sglang 0.5.10/0.5.14 and vllm 0.24.0 already cover these models (except l40s / partial rtx_pro on sglang).