From 0d6093fb6f1f08ed26beba0ce4ff1b0337a3efc5 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:19:01 +0200 Subject: [PATCH 01/69] dt-bindings: reset: add mt6572 resets Add a header for the resets on the mt6572 SoC. Signed-off-by: rva3 --- .../reset/mediatek,mt6572-resets.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt6572-resets.h diff --git a/include/dt-bindings/reset/mediatek,mt6572-resets.h b/include/dt-bindings/reset/mediatek,mt6572-resets.h new file mode 100644 index 00000000000000..c26b56ffc77e11 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6572-resets.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2026 rva3 + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6572 +#define _DT_BINDINGS_RESET_CONTROLLER_MT6572 + +#define MT6572_TOPRGU_INFRA_SW_RST 0 +#define MT6572_TOPRGU_MM_SW_RST 1 +#define MT6572_TOPRGU_MFG_SW_RST 2 +#define MT6572_TOPRGU_VENC_SW_RST 3 +#define MT6572_TOPRGU_VDEC_SW_RST 4 +#define MT6572_TOPRGU_IMG_SW_RST 5 +#define MT6572_TOPRGU_DDRPHY_SW_RST 6 +#define MT6572_TOPRGU_MD_SW_RST 7 +#define MT6572_TOPRGU_INFRA_AO_SW_RST 8 +#define MT6572_TOPRGU_MD_LITE_SW_RST 9 +#define MT6572_TOPRGU_APMIXED_SW_RST 10 +#define MT6572_TOPRGU_PWRAP_SPI_CTL_RST 11 +#define MT6572_TOPRGU_SW_RST_NUM 12 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6572 */ + From f9a157ca9802c9f7c992e5b871c88168e916e52e Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:19:34 +0200 Subject: [PATCH 02/69] dt-bindings: clock: add mt6572 Add a header for the clocks on the mt6572 SoC. Signed-off-by: rva3 --- .../dt-bindings/clock/mediatek,mt6572-clk.h | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6572-clk.h diff --git a/include/dt-bindings/clock/mediatek,mt6572-clk.h b/include/dt-bindings/clock/mediatek,mt6572-clk.h new file mode 100644 index 00000000000000..c56f5ed44d69d0 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6572-clk.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6572_H +#define _DT_BINDINGS_CLK_MT6572_H + +/* TOPCKGEN */ +#define CLK_TOP_SC_26M_SEL 0 +#define CLK_TOP_UNIV_48M_SEL 1 + +#define CLK_TOP_MPLL_D2 2 +#define CLK_TOP_MPLL_D3 3 +#define CLK_TOP_MPLL_D5 4 +#define CLK_TOP_MPLL_D7 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D6 7 +#define CLK_TOP_MPLL_D10 8 +#define CLK_TOP_MPLL_D8 9 +#define CLK_TOP_MPLL_D12 10 +#define CLK_TOP_MPLL_D20 11 +#define CLK_TOP_MPLL_D24 12 +#define CLK_TOP_UPLL_D2 13 +#define CLK_TOP_UPLL_D3 14 +#define CLK_TOP_UPLL_D5 15 +#define CLK_TOP_UPLL_D7 16 +#define CLK_TOP_UPLL_D4 17 +#define CLK_TOP_UPLL_D6 18 +#define CLK_TOP_UPLL_D10 19 +#define CLK_TOP_UPLL_D8 20 +#define CLK_TOP_UPLL_D12 21 +#define CLK_TOP_UPLL_D20 22 +#define CLK_TOP_UPLL_D16 23 +#define CLK_TOP_UPLL_D24 24 + +#define CLK_TOP_UART0_SEL 25 +#define CLK_TOP_EMI2X_SEL 26 +#define CLK_TOP_AXI_SEL 27 +#define CLK_TOP_MFG_SEL 28 +#define CLK_TOP_MSDC0_SEL 29 +#define CLK_TOP_SPI_NAND_SEL 30 +#define CLK_TOP_CAM_SEL 31 +#define CLK_TOP_PWM_SEL 32 +#define CLK_TOP_UART1_SEL 33 +#define CLK_TOP_MSDC1_SEL 34 +#define CLK_TOP_SPM_SEL 35 +#define CLK_TOP_PMIC_SPI_SEL 36 +#define CLK_TOP_AUDIO_INTBUS_SEL 37 + +#define CLK_TOP_PWM 38 +#define CLK_TOP_CAM 39 +#define CLK_TOP_MFG 40 +#define CLK_TOP_SPM 41 +#define CLK_TOP_UART0 42 +#define CLK_TOP_UART1 43 +#define CLK_TOP_MSDC0 44 +#define CLK_TOP_MSDC1 45 +#define CLK_TOP_PMIC_WRAP 46 +#define CLK_TOP_PMIC_SPI 47 +#define CLK_TOP_APXGPT 48 + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_WHPLL 3 + +#endif /* _DT_BINDINGS_CLK_MT6572_H */ From 8d6d5c975e48cc3ec1cbf6211b75910c0343f7aa Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:22:08 +0200 Subject: [PATCH 03/69] dt-bindings: pinctrl: add mt6572 pinfunc Add a header for the pinctrl on the mt6572 SoC. Signed-off-by: rva3 --- include/dt-bindings/pinctrl/mt6572-pinfunc.h | 833 +++++++++++++++++++ 1 file changed, 833 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6572-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6572-pinfunc.h b/include/dt-bindings/pinctrl/mt6572-pinfunc.h new file mode 100644 index 00000000000000..3628c82de2b6e3 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6572-pinfunc.h @@ -0,0 +1,833 @@ +#ifndef __DTS_MT6572_PINFUNC_H +#define __DTS_MT6572_PINFUNC_H + +#include + +#define MT6572_PIN_0_SIM2_SCLK__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6572_PIN_0_SIM2_SCLK__FUNC_SIM2_SCLK (MTK_PIN_NO(0) | 1) +#define MT6572_PIN_0_SIM2_SCLK__FUNC_SIM1_SCLK (MTK_PIN_NO(0) | 2) +#define MT6572_PIN_0_SIM2_SCLK__FUNC_CONN_MCU_TMS (MTK_PIN_NO(0) | 7) + +#define MT6572_PIN_1_SIM2_SIO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6572_PIN_1_SIM2_SIO__FUNC_SIM2_SIO (MTK_PIN_NO(1) | 1) +#define MT6572_PIN_1_SIM2_SIO__FUNC_SIM1_SIO (MTK_PIN_NO(1) | 2) +#define MT6572_PIN_1_SIM2_SIO__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(1) | 7) + +#define MT6572_PIN_2_SIM1_SCLK__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6572_PIN_2_SIM1_SCLK__FUNC_SIM1_SCLK (MTK_PIN_NO(2) | 1) +#define MT6572_PIN_2_SIM1_SCLK__FUNC_SIM2_SCLK (MTK_PIN_NO(2) | 2) +#define MT6572_PIN_2_SIM1_SCLK__FUNC_CONN_MCU_TDI (MTK_PIN_NO(2) | 7) + +#define MT6572_PIN_3_SIM1_SIO__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6572_PIN_3_SIM1_SIO__FUNC_SIM1_SIO (MTK_PIN_NO(3) | 1) +#define MT6572_PIN_3_SIM1_SIO__FUNC_SIM2_SIO (MTK_PIN_NO(3) | 2) +#define MT6572_PIN_3_SIM1_SIO__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 7) + +#define MT6572_PIN_4_AUD_CLK__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6572_PIN_4_AUD_CLK__FUNC_AUD_CLK (MTK_PIN_NO(4) | 1) +#define MT6572_PIN_4_AUD_CLK__FUNC_AUD_ADC_CK (MTK_PIN_NO(4) | 3) +#define MT6572_PIN_4_AUD_CLK__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(4) | 7) + +#define MT6572_PIN_5_AUD_MISO__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6572_PIN_5_AUD_MISO__FUNC_AUD_MISO (MTK_PIN_NO(5) | 1) +#define MT6572_PIN_5_AUD_MISO__FUNC_AUD_ADC_DAT_IN (MTK_PIN_NO(5) | 3) +#define MT6572_PIN_5_AUD_MISO__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(5) | 7) + +#define MT6572_PIN_6_AUD_MOSI__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6572_PIN_6_AUD_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(6) | 1) +#define MT6572_PIN_6_AUD_MOSI__FUNC_AUD_ADC_WS (MTK_PIN_NO(6) | 3) +#define MT6572_PIN_6_AUD_MOSI__FUNC_CONN_MCU_TDO (MTK_PIN_NO(6) | 7) + +#define MT6572_PIN_7_PMIC_EINT__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6572_PIN_7_PMIC_EINT__FUNC_PMIC_EINT (MTK_PIN_NO(7) | 1) + +#define MT6572_PIN_8_PMIC_SPI_CSN__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6572_PIN_8_PMIC_SPI_CSN__FUNC_PMIC_SPI_CSN (MTK_PIN_NO(8) | 1) + +#define MT6572_PIN_9_PMIC_SPI_SCK__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6572_PIN_9_PMIC_SPI_SCK__FUNC_PMIC_SPI_SCK (MTK_PIN_NO(9) | 1) + +#define MT6572_PIN_10_PMIC_SPI_MOSI__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6572_PIN_10_PMIC_SPI_MOSI__FUNC_PMIC_SPI_MOSI (MTK_PIN_NO(10) | 1) + +#define MT6572_PIN_11_PMIC_SPI_MISO__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6572_PIN_11_PMIC_SPI_MISO__FUNC_PMIC_SPI_MISO (MTK_PIN_NO(11) | 1) + +#define MT6572_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6572_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) + +#define MT6572_PIN_13_WATCHDOG__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6572_PIN_13_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(13) | 1) + +#define MT6572_PIN_14_LPD0__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6572_PIN_14_LPD0__FUNC_LPD0 (MTK_PIN_NO(14) | 1) +#define MT6572_PIN_14_LPD0__FUNC_PWM3 (MTK_PIN_NO(14) | 2) +#define MT6572_PIN_14_LPD0__FUNC_DPI_B0 (MTK_PIN_NO(14) | 4) +#define MT6572_PIN_14_LPD0__FUNC_DBG_OUT8 (MTK_PIN_NO(14) | 5) +#define MT6572_PIN_14_LPD0__FUNC_DBG_OUT0 (MTK_PIN_NO(14) | 6) +#define MT6572_PIN_14_LPD0__FUNC_CONN_MCU_TMS (MTK_PIN_NO(14) | 7) + +#define MT6572_PIN_15_LPD1__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6572_PIN_15_LPD1__FUNC_LPD1 (MTK_PIN_NO(15) | 1) +#define MT6572_PIN_15_LPD1__FUNC_PWM4 (MTK_PIN_NO(15) | 2) +#define MT6572_PIN_15_LPD1__FUNC_DPI_B1 (MTK_PIN_NO(15) | 4) +#define MT6572_PIN_15_LPD1__FUNC_DBG_OUT9 (MTK_PIN_NO(15) | 5) +#define MT6572_PIN_15_LPD1__FUNC_DBG_OUT1 (MTK_PIN_NO(15) | 6) +#define MT6572_PIN_15_LPD1__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(15) | 7) + +#define MT6572_PIN_16_LPD2__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6572_PIN_16_LPD2__FUNC_LPD2 (MTK_PIN_NO(16) | 1) +#define MT6572_PIN_16_LPD2__FUNC_PWM5 (MTK_PIN_NO(16) | 2) +#define MT6572_PIN_16_LPD2__FUNC_DPI_B2 (MTK_PIN_NO(16) | 4) +#define MT6572_PIN_16_LPD2__FUNC_DBG_OUT10 (MTK_PIN_NO(16) | 5) +#define MT6572_PIN_16_LPD2__FUNC_DBG_OUT2 (MTK_PIN_NO(16) | 6) +#define MT6572_PIN_16_LPD2__FUNC_CONN_MCU_TDI (MTK_PIN_NO(16) | 7) + +#define MT6572_PIN_17_LPD3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6572_PIN_17_LPD3__FUNC_LPD3 (MTK_PIN_NO(17) | 1) +#define MT6572_PIN_17_LPD3__FUNC_DPI_B3 (MTK_PIN_NO(17) | 4) +#define MT6572_PIN_17_LPD3__FUNC_DBG_OUT11 (MTK_PIN_NO(17) | 5) +#define MT6572_PIN_17_LPD3__FUNC_DBG_OUT3 (MTK_PIN_NO(17) | 6) +#define MT6572_PIN_17_LPD3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(17) | 7) + +#define MT6572_PIN_18_LPD4__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6572_PIN_18_LPD4__FUNC_LPD4 (MTK_PIN_NO(18) | 1) +#define MT6572_PIN_18_LPD4__FUNC_DPI_B4 (MTK_PIN_NO(18) | 4) +#define MT6572_PIN_18_LPD4__FUNC_DBG_OUT12 (MTK_PIN_NO(18) | 5) +#define MT6572_PIN_18_LPD4__FUNC_DBG_OUT4 (MTK_PIN_NO(18) | 6) +#define MT6572_PIN_18_LPD4__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 7) + +#define MT6572_PIN_19_LPD5__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6572_PIN_19_LPD5__FUNC_LPD5 (MTK_PIN_NO(19) | 1) +#define MT6572_PIN_19_LPD5__FUNC_DPI_B5 (MTK_PIN_NO(19) | 4) +#define MT6572_PIN_19_LPD5__FUNC_DBG_OUT13 (MTK_PIN_NO(19) | 5) +#define MT6572_PIN_19_LPD5__FUNC_DBG_OUT5 (MTK_PIN_NO(19) | 6) +#define MT6572_PIN_19_LPD5__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(19) | 7) + +#define MT6572_PIN_20_LPD6__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6572_PIN_20_LPD6__FUNC_LPD6 (MTK_PIN_NO(20) | 1) +#define MT6572_PIN_20_LPD6__FUNC_DPI_G0 (MTK_PIN_NO(20) | 4) +#define MT6572_PIN_20_LPD6__FUNC_DBG_OUT14 (MTK_PIN_NO(20) | 5) +#define MT6572_PIN_20_LPD6__FUNC_DBG_OUT6 (MTK_PIN_NO(20) | 6) +#define MT6572_PIN_20_LPD6__FUNC_CONN_MCU_TDO (MTK_PIN_NO(20) | 7) + +#define MT6572_PIN_21_LPD7__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6572_PIN_21_LPD7__FUNC_LPD7 (MTK_PIN_NO(21) | 1) +#define MT6572_PIN_21_LPD7__FUNC_KCOL7 (MTK_PIN_NO(21) | 3) +#define MT6572_PIN_21_LPD7__FUNC_DPI_G1 (MTK_PIN_NO(21) | 4) +#define MT6572_PIN_21_LPD7__FUNC_DBG_OUT15 (MTK_PIN_NO(21) | 5) +#define MT6572_PIN_21_LPD7__FUNC_DBG_OUT7 (MTK_PIN_NO(21) | 6) + +#define MT6572_PIN_22_LPD8__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6572_PIN_22_LPD8__FUNC_LPD8 (MTK_PIN_NO(22) | 1) +#define MT6572_PIN_22_LPD8__FUNC_PWM_BL (MTK_PIN_NO(22) | 2) +#define MT6572_PIN_22_LPD8__FUNC_DPI_G2 (MTK_PIN_NO(22) | 4) +#define MT6572_PIN_22_LPD8__FUNC_DBG_OUT8 (MTK_PIN_NO(22) | 6) +#define MT6572_PIN_22_LPD8__FUNC_CONN_GPIO0 (MTK_PIN_NO(22) | 7) + +#define MT6572_PIN_23_LPD9__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6572_PIN_23_LPD9__FUNC_LPD9 (MTK_PIN_NO(23) | 1) +#define MT6572_PIN_23_LPD9__FUNC_SRCLKENAI (MTK_PIN_NO(23) | 2) +#define MT6572_PIN_23_LPD9__FUNC_DPI_G3 (MTK_PIN_NO(23) | 4) +#define MT6572_PIN_23_LPD9__FUNC_DBG_OUT9 (MTK_PIN_NO(23) | 6) +#define MT6572_PIN_23_LPD9__FUNC_CONN_GPIO1 (MTK_PIN_NO(23) | 7) + +#define MT6572_PIN_24_LPD10__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6572_PIN_24_LPD10__FUNC_LPD10 (MTK_PIN_NO(24) | 1) +#define MT6572_PIN_24_LPD10__FUNC_MC1_INS (MTK_PIN_NO(24) | 2) +#define MT6572_PIN_24_LPD10__FUNC_DPI_G4 (MTK_PIN_NO(24) | 4) +#define MT6572_PIN_24_LPD10__FUNC_DBG_OUT10 (MTK_PIN_NO(24) | 6) +#define MT6572_PIN_24_LPD10__FUNC_CONN_GPIO2 (MTK_PIN_NO(24) | 7) + +#define MT6572_PIN_25_LPD11__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6572_PIN_25_LPD11__FUNC_LPD11 (MTK_PIN_NO(25) | 1) +#define MT6572_PIN_25_LPD11__FUNC_EINT5 (MTK_PIN_NO(25) | 2) +#define MT6572_PIN_25_LPD11__FUNC_DPI_G5 (MTK_PIN_NO(25) | 4) +#define MT6572_PIN_25_LPD11__FUNC_DBG_OUT11 (MTK_PIN_NO(25) | 6) +#define MT6572_PIN_25_LPD11__FUNC_CONN_GPIO3 (MTK_PIN_NO(25) | 7) + +#define MT6572_PIN_26_LPD12__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6572_PIN_26_LPD12__FUNC_LPD12 (MTK_PIN_NO(26) | 1) +#define MT6572_PIN_26_LPD12__FUNC_EINT4 (MTK_PIN_NO(26) | 2) +#define MT6572_PIN_26_LPD12__FUNC_DPI_R0 (MTK_PIN_NO(26) | 4) +#define MT6572_PIN_26_LPD12__FUNC_MD_EINT3 (MTK_PIN_NO(26) | 5) +#define MT6572_PIN_26_LPD12__FUNC_DBG_OUT12 (MTK_PIN_NO(26) | 6) +#define MT6572_PIN_26_LPD12__FUNC_CONN_GPIO4 (MTK_PIN_NO(26) | 7) + +#define MT6572_PIN_27_LPD13__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6572_PIN_27_LPD13__FUNC_LPD13 (MTK_PIN_NO(27) | 1) +#define MT6572_PIN_27_LPD13__FUNC_EINT3 (MTK_PIN_NO(27) | 2) +#define MT6572_PIN_27_LPD13__FUNC_DPI_R1 (MTK_PIN_NO(27) | 4) +#define MT6572_PIN_27_LPD13__FUNC_MD_EINT2 (MTK_PIN_NO(27) | 5) +#define MT6572_PIN_27_LPD13__FUNC_DBG_OUT13 (MTK_PIN_NO(27) | 6) +#define MT6572_PIN_27_LPD13__FUNC_CONN_GPIO5 (MTK_PIN_NO(27) | 7) + +#define MT6572_PIN_28_LPD14__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6572_PIN_28_LPD14__FUNC_LPD14 (MTK_PIN_NO(28) | 1) +#define MT6572_PIN_28_LPD14__FUNC_EINT2 (MTK_PIN_NO(28) | 2) +#define MT6572_PIN_28_LPD14__FUNC_DPI_R2 (MTK_PIN_NO(28) | 4) +#define MT6572_PIN_28_LPD14__FUNC_MD_EINT1 (MTK_PIN_NO(28) | 5) +#define MT6572_PIN_28_LPD14__FUNC_DBG_OUT14 (MTK_PIN_NO(28) | 6) +#define MT6572_PIN_28_LPD14__FUNC_CONN_GPIO6 (MTK_PIN_NO(28) | 7) + +#define MT6572_PIN_29_LPD15__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6572_PIN_29_LPD15__FUNC_LPD15 (MTK_PIN_NO(29) | 1) +#define MT6572_PIN_29_LPD15__FUNC_EINT1 (MTK_PIN_NO(29) | 2) +#define MT6572_PIN_29_LPD15__FUNC_DPI_R3 (MTK_PIN_NO(29) | 4) +#define MT6572_PIN_29_LPD15__FUNC_MD_EINT0 (MTK_PIN_NO(29) | 5) +#define MT6572_PIN_29_LPD15__FUNC_DBG_OUT15 (MTK_PIN_NO(29) | 6) +#define MT6572_PIN_29_LPD15__FUNC_CONN_GPIO7 (MTK_PIN_NO(29) | 7) + +#define MT6572_PIN_30_LPD16__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6572_PIN_30_LPD16__FUNC_LPD16 (MTK_PIN_NO(30) | 1) +#define MT6572_PIN_30_LPD16__FUNC_EINT0 (MTK_PIN_NO(30) | 2) +#define MT6572_PIN_30_LPD16__FUNC_PWM2 (MTK_PIN_NO(30) | 3) +#define MT6572_PIN_30_LPD16__FUNC_DPI_R4 (MTK_PIN_NO(30) | 4) +#define MT6572_PIN_30_LPD16__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(30) | 7) + +#define MT6572_PIN_31_LPD17__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6572_PIN_31_LPD17__FUNC_LPD17 (MTK_PIN_NO(31) | 1) +#define MT6572_PIN_31_LPD17__FUNC_EINT6 (MTK_PIN_NO(31) | 2) +#define MT6572_PIN_31_LPD17__FUNC_KROW7 (MTK_PIN_NO(31) | 3) +#define MT6572_PIN_31_LPD17__FUNC_DPI_R5 (MTK_PIN_NO(31) | 4) +#define MT6572_PIN_31_LPD17__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(31) | 7) + +#define MT6572_PIN_32_NFI0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6572_PIN_32_NFI0__FUNC_NFI0 (MTK_PIN_NO(32) | 4) +#define MT6572_PIN_32_NFI0__FUNC_CONN_MCU_TMS (MTK_PIN_NO(32) | 7) + +#define MT6572_PIN_33_NFI1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6572_PIN_33_NFI1__FUNC_NFI1 (MTK_PIN_NO(33) | 4) +#define MT6572_PIN_33_NFI1__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(33) | 7) + +#define MT6572_PIN_34_NFI2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6572_PIN_34_NFI2__FUNC_NFI2 (MTK_PIN_NO(34) | 4) +#define MT6572_PIN_34_NFI2__FUNC_CONN_MCU_TDI (MTK_PIN_NO(34) | 7) + +#define MT6572_PIN_35_NFI3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6572_PIN_35_NFI3__FUNC_NFI3 (MTK_PIN_NO(35) | 4) +#define MT6572_PIN_35_NFI3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(35) | 7) + +#define MT6572_PIN_36_NFI4__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6572_PIN_36_NFI4__FUNC_NFI4 (MTK_PIN_NO(36) | 4) +#define MT6572_PIN_36_NFI4__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(36) | 7) + +#define MT6572_PIN_37_NFI5__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6572_PIN_37_NFI5__FUNC_NFI5 (MTK_PIN_NO(37) | 4) +#define MT6572_PIN_37_NFI5__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(37) | 7) + +#define MT6572_PIN_38_NFI6__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6572_PIN_38_NFI6__FUNC_NFI6 (MTK_PIN_NO(38) | 4) +#define MT6572_PIN_38_NFI6__FUNC_CONN_MCU_TDO (MTK_PIN_NO(38) | 7) + +#define MT6572_PIN_39_NFI7__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6572_PIN_39_NFI7__FUNC_NFI7 (MTK_PIN_NO(39) | 4) + +#define MT6572_PIN_40_NFI8__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6572_PIN_40_NFI8__FUNC_NFI8 (MTK_PIN_NO(40) | 4) + +#define MT6572_PIN_41_NFI9__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6572_PIN_41_NFI9__FUNC_NFI9 (MTK_PIN_NO(41) | 4) + +#define MT6572_PIN_42_NFI10__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6572_PIN_42_NFI10__FUNC_NFI10 (MTK_PIN_NO(42) | 4) + +#define MT6572_PIN_43_NFI11__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6572_PIN_43_NFI11__FUNC_NFI11 (MTK_PIN_NO(43) | 4) + +#define MT6572_PIN_44_MC0_CK__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6572_PIN_44_MC0_CK__FUNC_MC0_CK (MTK_PIN_NO(44) | 1) +#define MT6572_PIN_44_MC0_CK__FUNC_LPTE (MTK_PIN_NO(44) | 3) +#define MT6572_PIN_44_MC0_CK__FUNC_NFI12 (MTK_PIN_NO(44) | 4) + +#define MT6572_PIN_45_MC0_CMD__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6572_PIN_45_MC0_CMD__FUNC_MC0_CMD (MTK_PIN_NO(45) | 1) +#define MT6572_PIN_45_MC0_CMD__FUNC_LPA0 (MTK_PIN_NO(45) | 3) +#define MT6572_PIN_45_MC0_CMD__FUNC_NFI13 (MTK_PIN_NO(45) | 4) + +#define MT6572_PIN_46_MC0_DAT0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6572_PIN_46_MC0_DAT0__FUNC_MC0_DAT0 (MTK_PIN_NO(46) | 1) +#define MT6572_PIN_46_MC0_DAT0__FUNC_LPWRB (MTK_PIN_NO(46) | 3) +#define MT6572_PIN_46_MC0_DAT0__FUNC_NFI14 (MTK_PIN_NO(46) | 4) + +#define MT6572_PIN_47_MC0_DAT1__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6572_PIN_47_MC0_DAT1__FUNC_MC0_DAT1 (MTK_PIN_NO(47) | 1) +#define MT6572_PIN_47_MC0_DAT1__FUNC_LPRDB (MTK_PIN_NO(47) | 3) +#define MT6572_PIN_47_MC0_DAT1__FUNC_NFI15 (MTK_PIN_NO(47) | 4) + +#define MT6572_PIN_48_MC0_DAT2__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6572_PIN_48_MC0_DAT2__FUNC_MC0_DAT2 (MTK_PIN_NO(48) | 1) +#define MT6572_PIN_48_MC0_DAT2__FUNC_NFI16 (MTK_PIN_NO(48) | 4) + +#define MT6572_PIN_49_MC0_DAT3__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT6572_PIN_49_MC0_DAT3__FUNC_MC0_DAT3 (MTK_PIN_NO(49) | 1) +#define MT6572_PIN_49_MC0_DAT3__FUNC_LPCE0B (MTK_PIN_NO(49) | 3) +#define MT6572_PIN_49_MC0_DAT3__FUNC_NFI17 (MTK_PIN_NO(49) | 4) + +#define MT6572_PIN_50_MC0_DAT4__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT6572_PIN_50_MC0_DAT4__FUNC_MC0_DAT4 (MTK_PIN_NO(50) | 1) +#define MT6572_PIN_50_MC0_DAT4__FUNC_PWM_BL (MTK_PIN_NO(50) | 2) +#define MT6572_PIN_50_MC0_DAT4__FUNC_NFI18 (MTK_PIN_NO(50) | 4) + +#define MT6572_PIN_51_MC0_DAT5__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT6572_PIN_51_MC0_DAT5__FUNC_MC0_DAT5 (MTK_PIN_NO(51) | 1) +#define MT6572_PIN_51_MC0_DAT5__FUNC_EINT13 (MTK_PIN_NO(51) | 2) +#define MT6572_PIN_51_MC0_DAT5__FUNC_NFI19 (MTK_PIN_NO(51) | 4) + +#define MT6572_PIN_52_MC0_DAT6__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT6572_PIN_52_MC0_DAT6__FUNC_MC0_DAT6 (MTK_PIN_NO(52) | 1) +#define MT6572_PIN_52_MC0_DAT6__FUNC_EINT14 (MTK_PIN_NO(52) | 2) +#define MT6572_PIN_52_MC0_DAT6__FUNC_NFI20 (MTK_PIN_NO(52) | 4) + +#define MT6572_PIN_53_MC0_DAT7__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT6572_PIN_53_MC0_DAT7__FUNC_MC0_DAT7 (MTK_PIN_NO(53) | 1) +#define MT6572_PIN_53_MC0_DAT7__FUNC_MC1_INS (MTK_PIN_NO(53) | 2) +#define MT6572_PIN_53_MC0_DAT7__FUNC_NFI21 (MTK_PIN_NO(53) | 4) + +#define MT6572_PIN_54_MC0_RSTB__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT6572_PIN_54_MC0_RSTB__FUNC_MC0_RSTB (MTK_PIN_NO(54) | 1) +#define MT6572_PIN_54_MC0_RSTB__FUNC_EINT12 (MTK_PIN_NO(54) | 2) +#define MT6572_PIN_54_MC0_RSTB__FUNC_LRSTB (MTK_PIN_NO(54) | 3) +#define MT6572_PIN_54_MC0_RSTB__FUNC_NFI22 (MTK_PIN_NO(54) | 4) + +#define MT6572_PIN_55_SD_DAT0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT6572_PIN_55_SD_DAT0__FUNC_SD_DAT0 (MTK_PIN_NO(55) | 1) +#define MT6572_PIN_55_SD_DAT0__FUNC_LPTE (MTK_PIN_NO(55) | 2) +#define MT6572_PIN_55_SD_DAT0__FUNC_SFCK (MTK_PIN_NO(55) | 3) +#define MT6572_PIN_55_SD_DAT0__FUNC_DPI_CK (MTK_PIN_NO(55) | 5) + +#define MT6572_PIN_56_SD_DAT1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT6572_PIN_56_SD_DAT1__FUNC_SD_DAT1 (MTK_PIN_NO(56) | 1) +#define MT6572_PIN_56_SD_DAT1__FUNC_LPA0 (MTK_PIN_NO(56) | 2) +#define MT6572_PIN_56_SD_DAT1__FUNC_SFCS1 (MTK_PIN_NO(56) | 3) +#define MT6572_PIN_56_SD_DAT1__FUNC_EINT10 (MTK_PIN_NO(56) | 4) +#define MT6572_PIN_56_SD_DAT1__FUNC_DPI_DE (MTK_PIN_NO(56) | 5) + +#define MT6572_PIN_57_SD_DAT2__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT6572_PIN_57_SD_DAT2__FUNC_SD_DAT2 (MTK_PIN_NO(57) | 1) +#define MT6572_PIN_57_SD_DAT2__FUNC_LPWRB (MTK_PIN_NO(57) | 2) +#define MT6572_PIN_57_SD_DAT2__FUNC_SFIN (MTK_PIN_NO(57) | 3) +#define MT6572_PIN_57_SD_DAT2__FUNC_EINT11 (MTK_PIN_NO(57) | 4) +#define MT6572_PIN_57_SD_DAT2__FUNC_DPI_VSYNC (MTK_PIN_NO(57) | 5) + +#define MT6572_PIN_58_SD_DAT3__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT6572_PIN_58_SD_DAT3__FUNC_SD_DAT3 (MTK_PIN_NO(58) | 1) +#define MT6572_PIN_58_SD_DAT3__FUNC_LPRDB (MTK_PIN_NO(58) | 2) +#define MT6572_PIN_58_SD_DAT3__FUNC_SFHOLD (MTK_PIN_NO(58) | 3) +#define MT6572_PIN_58_SD_DAT3__FUNC_EINT12 (MTK_PIN_NO(58) | 4) +#define MT6572_PIN_58_SD_DAT3__FUNC_DPI_HSYNC (MTK_PIN_NO(58) | 5) + +#define MT6572_PIN_59_SD_CK__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT6572_PIN_59_SD_CK__FUNC_SD_CK (MTK_PIN_NO(59) | 1) +#define MT6572_PIN_59_SD_CK__FUNC_LRSTB (MTK_PIN_NO(59) | 2) +#define MT6572_PIN_59_SD_CK__FUNC_SFOUT (MTK_PIN_NO(59) | 3) + +#define MT6572_PIN_60_SD_CMD__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT6572_PIN_60_SD_CMD__FUNC_SD_CMD (MTK_PIN_NO(60) | 1) +#define MT6572_PIN_60_SD_CMD__FUNC_LPCE0B (MTK_PIN_NO(60) | 2) +#define MT6572_PIN_60_SD_CMD__FUNC_SFWP_B (MTK_PIN_NO(60) | 3) +#define MT6572_PIN_60_SD_CMD__FUNC_EINT9 (MTK_PIN_NO(60) | 4) +#define MT6572_PIN_60_SD_CMD__FUNC_LSCE0B (MTK_PIN_NO(60) | 5) + +#define MT6572_PIN_61_CMPCLK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT6572_PIN_61_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(61) | 1) +#define MT6572_PIN_61_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(61) | 2) +#define MT6572_PIN_61_CMPCLK__FUNC_DBG_OUT0 (MTK_PIN_NO(61) | 6) + +#define MT6572_PIN_62_CMMCLK__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT6572_PIN_62_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(62) | 1) +#define MT6572_PIN_62_CMMCLK__FUNC_DBG_OUT1 (MTK_PIN_NO(62) | 6) + +#define MT6572_PIN_63_CMDAT0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT6572_PIN_63_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(63) | 1) +#define MT6572_PIN_63_CMDAT0__FUNC_EINT3 (MTK_PIN_NO(63) | 3) +#define MT6572_PIN_63_CMDAT0__FUNC_TDD_TXD (MTK_PIN_NO(63) | 5) +#define MT6572_PIN_63_CMDAT0__FUNC_DBG_OUT2 (MTK_PIN_NO(63) | 6) +#define MT6572_PIN_63_CMDAT0__FUNC_CONN_GPIO16 (MTK_PIN_NO(63) | 7) + +#define MT6572_PIN_64_CMDAT1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT6572_PIN_64_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(64) | 1) +#define MT6572_PIN_64_CMDAT1__FUNC_EINT13 (MTK_PIN_NO(64) | 3) +#define MT6572_PIN_64_CMDAT1__FUNC_MD_DSPJTD (MTK_PIN_NO(64) | 5) +#define MT6572_PIN_64_CMDAT1__FUNC_DBG_OUT3 (MTK_PIN_NO(64) | 6) +#define MT6572_PIN_64_CMDAT1__FUNC_CONN_GPIO17 (MTK_PIN_NO(64) | 7) + +#define MT6572_PIN_65_CMDAT2__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT6572_PIN_65_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(65) | 1) +#define MT6572_PIN_65_CMDAT2__FUNC_EINT7 (MTK_PIN_NO(65) | 3) +#define MT6572_PIN_65_CMDAT2__FUNC_MD_DSPJTCK (MTK_PIN_NO(65) | 5) +#define MT6572_PIN_65_CMDAT2__FUNC_DBG_OUT4 (MTK_PIN_NO(65) | 6) +#define MT6572_PIN_65_CMDAT2__FUNC_CONN_GPIO18 (MTK_PIN_NO(65) | 7) + +#define MT6572_PIN_66_CMDAT3__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT6572_PIN_66_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(66) | 1) +#define MT6572_PIN_66_CMDAT3__FUNC_EINT8 (MTK_PIN_NO(66) | 3) +#define MT6572_PIN_66_CMDAT3__FUNC_MD_DSPJTMS (MTK_PIN_NO(66) | 5) +#define MT6572_PIN_66_CMDAT3__FUNC_DBG_OUT5 (MTK_PIN_NO(66) | 6) +#define MT6572_PIN_66_CMDAT3__FUNC_CONN_GPIO19 (MTK_PIN_NO(66) | 7) + +#define MT6572_PIN_67_MIPI_RDP0_A__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT6572_PIN_67_MIPI_RDP0_A__FUNC_MIPI_RDP0_A (MTK_PIN_NO(67) | 1) +#define MT6572_PIN_67_MIPI_RDP0_A__FUNC_CMDAT4 (MTK_PIN_NO(67) | 2) +#define MT6572_PIN_67_MIPI_RDP0_A__FUNC_MC1_INS (MTK_PIN_NO(67) | 3) + +#define MT6572_PIN_68_MIPI_RDN0_A__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT6572_PIN_68_MIPI_RDN0_A__FUNC_MIPI_RDN0_A (MTK_PIN_NO(68) | 1) +#define MT6572_PIN_68_MIPI_RDN0_A__FUNC_CMDAT5 (MTK_PIN_NO(68) | 2) +#define MT6572_PIN_68_MIPI_RDN0_A__FUNC_KCOL3 (MTK_PIN_NO(68) | 3) + +#define MT6572_PIN_69_MIPI_RDP1_A__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT6572_PIN_69_MIPI_RDP1_A__FUNC_MIPI_RDP1_A (MTK_PIN_NO(69) | 1) +#define MT6572_PIN_69_MIPI_RDP1_A__FUNC_CMDAT6 (MTK_PIN_NO(69) | 2) +#define MT6572_PIN_69_MIPI_RDP1_A__FUNC_KCOL4 (MTK_PIN_NO(69) | 3) +#define MT6572_PIN_69_MIPI_RDP1_A__FUNC_EINT7 (MTK_PIN_NO(69) | 4) + +#define MT6572_PIN_70_MIPI_RDN1_A__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT6572_PIN_70_MIPI_RDN1_A__FUNC_MIPI_RDN1_A (MTK_PIN_NO(70) | 1) +#define MT6572_PIN_70_MIPI_RDN1_A__FUNC_CMDAT7 (MTK_PIN_NO(70) | 2) +#define MT6572_PIN_70_MIPI_RDN1_A__FUNC_KCOL5 (MTK_PIN_NO(70) | 3) +#define MT6572_PIN_70_MIPI_RDN1_A__FUNC_EINT8 (MTK_PIN_NO(70) | 4) + +#define MT6572_PIN_71_MIPI_RCP_A__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT6572_PIN_71_MIPI_RCP_A__FUNC_MIPI_RCP_A (MTK_PIN_NO(71) | 1) +#define MT6572_PIN_71_MIPI_RCP_A__FUNC_CMHSYNC (MTK_PIN_NO(71) | 2) +#define MT6572_PIN_71_MIPI_RCP_A__FUNC_KCOL6 (MTK_PIN_NO(71) | 3) + +#define MT6572_PIN_72_MIPI_RCN_A__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT6572_PIN_72_MIPI_RCN_A__FUNC_MIPI_RCN_A (MTK_PIN_NO(72) | 1) +#define MT6572_PIN_72_MIPI_RCN_A__FUNC_CMVSYNC (MTK_PIN_NO(72) | 2) +#define MT6572_PIN_72_MIPI_RCN_A__FUNC_KCOL7 (MTK_PIN_NO(72) | 3) + +#define MT6572_PIN_73_MIPI_RDP0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT6572_PIN_73_MIPI_RDP0__FUNC_MIPI_RDP0 (MTK_PIN_NO(73) | 1) +#define MT6572_PIN_73_MIPI_RDP0__FUNC_EINT3 (MTK_PIN_NO(73) | 3) +#define MT6572_PIN_73_MIPI_RDP0__FUNC_MC1_INS (MTK_PIN_NO(73) | 4) + +#define MT6572_PIN_74_MIPI_RDN0__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT6572_PIN_74_MIPI_RDN0__FUNC_MIPI_RDN0 (MTK_PIN_NO(74) | 1) +#define MT6572_PIN_74_MIPI_RDN0__FUNC_EINT4 (MTK_PIN_NO(74) | 3) +#define MT6572_PIN_74_MIPI_RDN0__FUNC_KCOL3 (MTK_PIN_NO(74) | 4) + +#define MT6572_PIN_75_MIPI_RDP1__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT6572_PIN_75_MIPI_RDP1__FUNC_MIPI_RDP1 (MTK_PIN_NO(75) | 1) +#define MT6572_PIN_75_MIPI_RDP1__FUNC_EINT7 (MTK_PIN_NO(75) | 3) +#define MT6572_PIN_75_MIPI_RDP1__FUNC_KCOL4 (MTK_PIN_NO(75) | 4) + +#define MT6572_PIN_76_MIPI_RDN1__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT6572_PIN_76_MIPI_RDN1__FUNC_MIPI_RDN1 (MTK_PIN_NO(76) | 1) +#define MT6572_PIN_76_MIPI_RDN1__FUNC_EINT8 (MTK_PIN_NO(76) | 3) +#define MT6572_PIN_76_MIPI_RDN1__FUNC_KCOL5 (MTK_PIN_NO(76) | 4) + +#define MT6572_PIN_77_MIPI_RCP__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT6572_PIN_77_MIPI_RCP__FUNC_MIPI_RCP (MTK_PIN_NO(77) | 1) +#define MT6572_PIN_77_MIPI_RCP__FUNC_EINT6 (MTK_PIN_NO(77) | 2) +#define MT6572_PIN_77_MIPI_RCP__FUNC_MC1_INS (MTK_PIN_NO(77) | 3) +#define MT6572_PIN_77_MIPI_RCP__FUNC_KCOL6 (MTK_PIN_NO(77) | 4) + +#define MT6572_PIN_78_MIPI_RCN__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT6572_PIN_78_MIPI_RCN__FUNC_MIPI_RCN (MTK_PIN_NO(78) | 1) +#define MT6572_PIN_78_MIPI_RCN__FUNC_SRCLKENAI (MTK_PIN_NO(78) | 3) +#define MT6572_PIN_78_MIPI_RCN__FUNC_KCOL7 (MTK_PIN_NO(78) | 4) + +#define MT6572_PIN_79_MIPI_TDP0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT6572_PIN_79_MIPI_TDP0__FUNC_MIPI_TDP0 (MTK_PIN_NO(79) | 1) +#define MT6572_PIN_79_MIPI_TDP0__FUNC_EINT9 (MTK_PIN_NO(79) | 3) + +#define MT6572_PIN_80_MIPI_TDN0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT6572_PIN_80_MIPI_TDN0__FUNC_MIPI_TDN0 (MTK_PIN_NO(80) | 1) +#define MT6572_PIN_80_MIPI_TDN0__FUNC_EINT10 (MTK_PIN_NO(80) | 3) + +#define MT6572_PIN_81_MIPI_TDP1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT6572_PIN_81_MIPI_TDP1__FUNC_MIPI_TDP1 (MTK_PIN_NO(81) | 1) +#define MT6572_PIN_81_MIPI_TDP1__FUNC_EINT11 (MTK_PIN_NO(81) | 3) + +#define MT6572_PIN_82_MIPI_TDN1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT6572_PIN_82_MIPI_TDN1__FUNC_MIPI_TDN1 (MTK_PIN_NO(82) | 1) +#define MT6572_PIN_82_MIPI_TDN1__FUNC_EINT12 (MTK_PIN_NO(82) | 3) + +#define MT6572_PIN_83_MIPI_TCP__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT6572_PIN_83_MIPI_TCP__FUNC_MIPI_TCP (MTK_PIN_NO(83) | 1) +#define MT6572_PIN_83_MIPI_TCP__FUNC_EINT13 (MTK_PIN_NO(83) | 3) + +#define MT6572_PIN_84_MIPI_TCN__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT6572_PIN_84_MIPI_TCN__FUNC_MIPI_TCN (MTK_PIN_NO(84) | 1) +#define MT6572_PIN_84_MIPI_TCN__FUNC_EINT14 (MTK_PIN_NO(84) | 3) +#define MT6572_PIN_84_MIPI_TCN__FUNC_SRCLKENAI (MTK_PIN_NO(84) | 4) + +#define MT6572_PIN_85_MIPI_TDP2__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT6572_PIN_85_MIPI_TDP2__FUNC_MIPI_TDP2 (MTK_PIN_NO(85) | 1) +#define MT6572_PIN_85_MIPI_TDP2__FUNC_MD_EINT0 (MTK_PIN_NO(85) | 3) + +#define MT6572_PIN_86_MIPI_TDN2__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT6572_PIN_86_MIPI_TDN2__FUNC_MIPI_TDN2 (MTK_PIN_NO(86) | 1) +#define MT6572_PIN_86_MIPI_TDN2__FUNC_MD_EINT1 (MTK_PIN_NO(86) | 3) +#define MT6572_PIN_86_MIPI_TDN2__FUNC_MC1_INS (MTK_PIN_NO(86) | 4) + +#define MT6572_PIN_87_EINT8__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT6572_PIN_87_EINT8__FUNC_EINT8 (MTK_PIN_NO(87) | 1) +#define MT6572_PIN_87_EINT8__FUNC_SFCS2 (MTK_PIN_NO(87) | 2) +#define MT6572_PIN_87_EINT8__FUNC_KCOL3 (MTK_PIN_NO(87) | 3) +#define MT6572_PIN_87_EINT8__FUNC_TDD_TXD (MTK_PIN_NO(87) | 4) +#define MT6572_PIN_87_EINT8__FUNC_JTCK (MTK_PIN_NO(87) | 5) +#define MT6572_PIN_87_EINT8__FUNC_DBG_OUT6 (MTK_PIN_NO(87) | 6) +#define MT6572_PIN_87_EINT8__FUNC_CONN_GPIO20 (MTK_PIN_NO(87) | 7) + +#define MT6572_PIN_88_EINT9__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT6572_PIN_88_EINT9__FUNC_EINT9 (MTK_PIN_NO(88) | 1) +#define MT6572_PIN_88_EINT9__FUNC_MC1_INS (MTK_PIN_NO(88) | 2) +#define MT6572_PIN_88_EINT9__FUNC_KCOL4 (MTK_PIN_NO(88) | 3) +#define MT6572_PIN_88_EINT9__FUNC_JTMS (MTK_PIN_NO(88) | 5) +#define MT6572_PIN_88_EINT9__FUNC_DBG_OUT7 (MTK_PIN_NO(88) | 6) +#define MT6572_PIN_88_EINT9__FUNC_CONN_GPIO21 (MTK_PIN_NO(88) | 7) + +#define MT6572_PIN_89_EINT14__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT6572_PIN_89_EINT14__FUNC_EINT14 (MTK_PIN_NO(89) | 1) +#define MT6572_PIN_89_EINT14__FUNC_SCL_1_1 (MTK_PIN_NO(89) | 2) +#define MT6572_PIN_89_EINT14__FUNC_KROW7 (MTK_PIN_NO(89) | 3) +#define MT6572_PIN_89_EINT14__FUNC_SIM1_SRST (MTK_PIN_NO(89) | 4) +#define MT6572_PIN_89_EINT14__FUNC_JTDI (MTK_PIN_NO(89) | 5) +#define MT6572_PIN_89_EINT14__FUNC_DBG_OUT8 (MTK_PIN_NO(89) | 6) +#define MT6572_PIN_89_EINT14__FUNC_CONN_GPIO22 (MTK_PIN_NO(89) | 7) + +#define MT6572_PIN_90_EINT15__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT6572_PIN_90_EINT15__FUNC_EINT15 (MTK_PIN_NO(90) | 1) +#define MT6572_PIN_90_EINT15__FUNC_SDA_1_1 (MTK_PIN_NO(90) | 2) +#define MT6572_PIN_90_EINT15__FUNC_KCOL7 (MTK_PIN_NO(90) | 3) +#define MT6572_PIN_90_EINT15__FUNC_SIM2_SRST (MTK_PIN_NO(90) | 4) +#define MT6572_PIN_90_EINT15__FUNC_JTDO (MTK_PIN_NO(90) | 5) +#define MT6572_PIN_90_EINT15__FUNC_DBG_OUT9 (MTK_PIN_NO(90) | 6) +#define MT6572_PIN_90_EINT15__FUNC_CONN_GPIO23 (MTK_PIN_NO(90) | 7) + +#define MT6572_PIN_91_MC1_CK__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT6572_PIN_91_MC1_CK__FUNC_MC1_CK (MTK_PIN_NO(91) | 1) +#define MT6572_PIN_91_MC1_CK__FUNC_JTMS (MTK_PIN_NO(91) | 4) +#define MT6572_PIN_91_MC1_CK__FUNC_TDD_TMS (MTK_PIN_NO(91) | 5) +#define MT6572_PIN_91_MC1_CK__FUNC_CONN_DSP_JDI (MTK_PIN_NO(91) | 7) + +#define MT6572_PIN_92_MC1_CMD__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT6572_PIN_92_MC1_CMD__FUNC_MC1_CMD (MTK_PIN_NO(92) | 1) +#define MT6572_PIN_92_MC1_CMD__FUNC_TDD_TRSTN (MTK_PIN_NO(92) | 5) +#define MT6572_PIN_92_MC1_CMD__FUNC_CONN_DSP_JDO (MTK_PIN_NO(92) | 7) + +#define MT6572_PIN_93_MC1_DAT0__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT6572_PIN_93_MC1_DAT0__FUNC_MC1_DAT0 (MTK_PIN_NO(93) | 1) +#define MT6572_PIN_93_MC1_DAT0__FUNC_JTCK (MTK_PIN_NO(93) | 4) +#define MT6572_PIN_93_MC1_DAT0__FUNC_TDD_TCK (MTK_PIN_NO(93) | 5) +#define MT6572_PIN_93_MC1_DAT0__FUNC_CONN_DSP_JCK (MTK_PIN_NO(93) | 7) + +#define MT6572_PIN_94_MC1_DAT1__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT6572_PIN_94_MC1_DAT1__FUNC_MC1_DAT1 (MTK_PIN_NO(94) | 1) +#define MT6572_PIN_94_MC1_DAT1__FUNC_DAI_RX_GPIO (MTK_PIN_NO(94) | 5) +#define MT6572_PIN_94_MC1_DAT1__FUNC_TDD_TXD (MTK_PIN_NO(94) | 6) + +#define MT6572_PIN_95_MC1_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT6572_PIN_95_MC1_DAT2__FUNC_MC1_DAT2 (MTK_PIN_NO(95) | 1) +#define MT6572_PIN_95_MC1_DAT2__FUNC_JTDI (MTK_PIN_NO(95) | 4) +#define MT6572_PIN_95_MC1_DAT2__FUNC_TDD_TDI (MTK_PIN_NO(95) | 5) +#define MT6572_PIN_95_MC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(95) | 7) + +#define MT6572_PIN_96_MC1_DAT3__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT6572_PIN_96_MC1_DAT3__FUNC_MC1_DAT3 (MTK_PIN_NO(96) | 1) +#define MT6572_PIN_96_MC1_DAT3__FUNC_JTDO (MTK_PIN_NO(96) | 4) +#define MT6572_PIN_96_MC1_DAT3__FUNC_TDD_TDO (MTK_PIN_NO(96) | 5) +#define MT6572_PIN_96_MC1_DAT3__FUNC_CONN_DSP_JMS (MTK_PIN_NO(96) | 7) + +#define MT6572_PIN_97_SPI_CS__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT6572_PIN_97_SPI_CS__FUNC_SPI_CS (MTK_PIN_NO(97) | 1) +#define MT6572_PIN_97_SPI_CS__FUNC_I2S_IN_WS (MTK_PIN_NO(97) | 2) +#define MT6572_PIN_97_SPI_CS__FUNC_KROW3 (MTK_PIN_NO(97) | 3) +#define MT6572_PIN_97_SPI_CS__FUNC_EINT3 (MTK_PIN_NO(97) | 4) +#define MT6572_PIN_97_SPI_CS__FUNC_DPI_B6 (MTK_PIN_NO(97) | 5) +#define MT6572_PIN_97_SPI_CS__FUNC_DBG_OUT0 (MTK_PIN_NO(97) | 6) +#define MT6572_PIN_97_SPI_CS__FUNC_MD_CDMA_GPS_SYNC (MTK_PIN_NO(97) | 7) + +#define MT6572_PIN_98_SPI_SCK__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT6572_PIN_98_SPI_SCK__FUNC_SPI_SCK (MTK_PIN_NO(98) | 1) +#define MT6572_PIN_98_SPI_SCK__FUNC_I2S_IN_CK (MTK_PIN_NO(98) | 2) +#define MT6572_PIN_98_SPI_SCK__FUNC_KROW4 (MTK_PIN_NO(98) | 3) +#define MT6572_PIN_98_SPI_SCK__FUNC_EINT4 (MTK_PIN_NO(98) | 4) +#define MT6572_PIN_98_SPI_SCK__FUNC_DPI_B7 (MTK_PIN_NO(98) | 5) +#define MT6572_PIN_98_SPI_SCK__FUNC_DBG_OUT1 (MTK_PIN_NO(98) | 6) +#define MT6572_PIN_98_SPI_SCK__FUNC_MD_EXT_FRAME_SYNC (MTK_PIN_NO(98) | 7) + +#define MT6572_PIN_99_SPI_MOSI__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT6572_PIN_99_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(99) | 1) +#define MT6572_PIN_99_SPI_MOSI__FUNC_I2S_IN_DAT (MTK_PIN_NO(99) | 2) +#define MT6572_PIN_99_SPI_MOSI__FUNC_KROW5 (MTK_PIN_NO(99) | 3) +#define MT6572_PIN_99_SPI_MOSI__FUNC_EINT7 (MTK_PIN_NO(99) | 4) +#define MT6572_PIN_99_SPI_MOSI__FUNC_DPI_G6 (MTK_PIN_NO(99) | 5) +#define MT6572_PIN_99_SPI_MOSI__FUNC_DBG_OUT2 (MTK_PIN_NO(99) | 6) + +#define MT6572_PIN_100_SPI_MISO__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT6572_PIN_100_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(100) | 1) +#define MT6572_PIN_100_SPI_MISO__FUNC_SRCLKENAI (MTK_PIN_NO(100) | 2) +#define MT6572_PIN_100_SPI_MISO__FUNC_KROW6 (MTK_PIN_NO(100) | 3) +#define MT6572_PIN_100_SPI_MISO__FUNC_EINT14 (MTK_PIN_NO(100) | 4) +#define MT6572_PIN_100_SPI_MISO__FUNC_DPI_G7 (MTK_PIN_NO(100) | 5) +#define MT6572_PIN_100_SPI_MISO__FUNC_DBG_OUT3 (MTK_PIN_NO(100) | 6) + +#define MT6572_PIN_101_URXD2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT6572_PIN_101_URXD2__FUNC_URXD2 (MTK_PIN_NO(101) | 1) +#define MT6572_PIN_101_URXD2__FUNC_EINT15 (MTK_PIN_NO(101) | 2) +#define MT6572_PIN_101_URXD2__FUNC_SCL_1_2 (MTK_PIN_NO(101) | 3) +#define MT6572_PIN_101_URXD2__FUNC_JTCK (MTK_PIN_NO(101) | 4) +#define MT6572_PIN_101_URXD2__FUNC_DPI_R6 (MTK_PIN_NO(101) | 5) + +#define MT6572_PIN_102_UTXD2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT6572_PIN_102_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(102) | 1) +#define MT6572_PIN_102_UTXD2__FUNC_PWM_BL (MTK_PIN_NO(102) | 2) +#define MT6572_PIN_102_UTXD2__FUNC_SDA_1_2 (MTK_PIN_NO(102) | 3) +#define MT6572_PIN_102_UTXD2__FUNC_JTMS (MTK_PIN_NO(102) | 4) +#define MT6572_PIN_102_UTXD2__FUNC_DPI_R7 (MTK_PIN_NO(102) | 5) + +#define MT6572_PIN_103_URXD1__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT6572_PIN_103_URXD1__FUNC_URXD1 (MTK_PIN_NO(103) | 1) +#define MT6572_PIN_103_URXD1__FUNC_MD_URXD (MTK_PIN_NO(103) | 5) +#define MT6572_PIN_103_URXD1__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(103) | 7) + +#define MT6572_PIN_104_UTXD1__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT6572_PIN_104_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(104) | 1) +#define MT6572_PIN_104_UTXD1__FUNC_MD_UTXD (MTK_PIN_NO(104) | 5) +#define MT6572_PIN_104_UTXD1__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(104) | 7) + +#define MT6572_PIN_105_SCL_0_0__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT6572_PIN_105_SCL_0_0__FUNC_SCL_0_0 (MTK_PIN_NO(105) | 1) + +#define MT6572_PIN_106_SDA_0_0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT6572_PIN_106_SDA_0_0__FUNC_SDA_0_0 (MTK_PIN_NO(106) | 1) + +#define MT6572_PIN_107_KCOL0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT6572_PIN_107_KCOL0__FUNC_KCOL0 (MTK_PIN_NO(107) | 1) +#define MT6572_PIN_107_KCOL0__FUNC_DBG_OUT10 (MTK_PIN_NO(107) | 6) +#define MT6572_PIN_107_KCOL0__FUNC_CONN_GPIO24 (MTK_PIN_NO(107) | 7) + +#define MT6572_PIN_108_KCOL1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT6572_PIN_108_KCOL1__FUNC_KCOL1 (MTK_PIN_NO(108) | 1) +#define MT6572_PIN_108_KCOL1__FUNC_EINT6 (MTK_PIN_NO(108) | 2) +#define MT6572_PIN_108_KCOL1__FUNC_PWM2 (MTK_PIN_NO(108) | 3) +#define MT6572_PIN_108_KCOL1__FUNC_MD_URXD (MTK_PIN_NO(108) | 5) +#define MT6572_PIN_108_KCOL1__FUNC_DBG_OUT11 (MTK_PIN_NO(108) | 6) +#define MT6572_PIN_108_KCOL1__FUNC_CONN_GPIO25 (MTK_PIN_NO(108) | 7) + +#define MT6572_PIN_109_KCOL2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT6572_PIN_109_KCOL2__FUNC_KCOL2 (MTK_PIN_NO(109) | 1) +#define MT6572_PIN_109_KCOL2__FUNC_JTCK (MTK_PIN_NO(109) | 4) +#define MT6572_PIN_109_KCOL2__FUNC_DBG_OUT12 (MTK_PIN_NO(109) | 6) +#define MT6572_PIN_109_KCOL2__FUNC_CONN_GPIO26 (MTK_PIN_NO(109) | 7) + +#define MT6572_PIN_110_KROW0__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT6572_PIN_110_KROW0__FUNC_KROW0 (MTK_PIN_NO(110) | 1) +#define MT6572_PIN_110_KROW0__FUNC_DBG_OUT13 (MTK_PIN_NO(110) | 6) +#define MT6572_PIN_110_KROW0__FUNC_CONN_GPIO27 (MTK_PIN_NO(110) | 7) + +#define MT6572_PIN_111_KROW1__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT6572_PIN_111_KROW1__FUNC_KROW1 (MTK_PIN_NO(111) | 1) +#define MT6572_PIN_111_KROW1__FUNC_LPTE_2ND (MTK_PIN_NO(111) | 2) +#define MT6572_PIN_111_KROW1__FUNC_PWM1 (MTK_PIN_NO(111) | 3) +#define MT6572_PIN_111_KROW1__FUNC_MD_UTXD (MTK_PIN_NO(111) | 5) +#define MT6572_PIN_111_KROW1__FUNC_DBG_OUT14 (MTK_PIN_NO(111) | 6) +#define MT6572_PIN_111_KROW1__FUNC_CONN_GPIO28 (MTK_PIN_NO(111) | 7) + +#define MT6572_PIN_112_KROW2__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT6572_PIN_112_KROW2__FUNC_KROW2 (MTK_PIN_NO(112) | 1) +#define MT6572_PIN_112_KROW2__FUNC_JTMS (MTK_PIN_NO(112) | 4) +#define MT6572_PIN_112_KROW2__FUNC_DBG_OUT15 (MTK_PIN_NO(112) | 6) +#define MT6572_PIN_112_KROW2__FUNC_CONN_GPIO29 (MTK_PIN_NO(112) | 7) + +#define MT6572_PIN_113_SCL_1_0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT6572_PIN_113_SCL_1_0__FUNC_SCL_1_0 (MTK_PIN_NO(113) | 1) + +#define MT6572_PIN_114_SDA_1_0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT6572_PIN_114_SDA_1_0__FUNC_SDA_1_0 (MTK_PIN_NO(114) | 1) + +#define MT6572_PIN_115_CONN_WB_CTRL5__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT6572_PIN_115_CONN_WB_CTRL5__FUNC_CONN_WB_CTRL5 (MTK_PIN_NO(115) | 1) + +#define MT6572_PIN_116_CONN_WB_CTRL4__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT6572_PIN_116_CONN_WB_CTRL4__FUNC_CONN_WB_CTRL4 (MTK_PIN_NO(116) | 1) + +#define MT6572_PIN_117_CONN_WB_CTRL3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT6572_PIN_117_CONN_WB_CTRL3__FUNC_CONN_WB_CTRL3 (MTK_PIN_NO(117) | 1) + +#define MT6572_PIN_118_CONN_WB_CTRL2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT6572_PIN_118_CONN_WB_CTRL2__FUNC_CONN_WB_CTRL2 (MTK_PIN_NO(118) | 1) + +#define MT6572_PIN_119_CONN_WB_CTRL1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT6572_PIN_119_CONN_WB_CTRL1__FUNC_CONN_WB_CTRL1 (MTK_PIN_NO(119) | 1) + +#define MT6572_PIN_120_CONN_WB_CTRL0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT6572_PIN_120_CONN_WB_CTRL0__FUNC_CONN_WB_CTRL0 (MTK_PIN_NO(120) | 1) + +#define MT6572_PIN_121_CONN_SEN__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT6572_PIN_121_CONN_SEN__FUNC_CONN_SEN (MTK_PIN_NO(121) | 1) + +#define MT6572_PIN_122_CONN_SDATA__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT6572_PIN_122_CONN_SDATA__FUNC_CONN_SDATA (MTK_PIN_NO(122) | 1) + +#define MT6572_PIN_123_CONN_SCLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT6572_PIN_123_CONN_SCLK__FUNC_CONN_SCLK (MTK_PIN_NO(123) | 1) + +#define MT6572_PIN_124_CONN_RSTB__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT6572_PIN_124_CONN_RSTB__FUNC_CONN_RSTB (MTK_PIN_NO(124) | 1) + +#define MT6572_PIN_126_CONN_F2W_CK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT6572_PIN_126_CONN_F2W_CK__FUNC_CONN_F2W_CK (MTK_PIN_NO(126) | 1) + +#define MT6572_PIN_127_CONN_F2W_DAT__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT6572_PIN_127_CONN_F2W_DAT__FUNC_CONN_F2W_DAT (MTK_PIN_NO(127) | 1) + +#define MT6572_PIN_128_PWM1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT6572_PIN_128_PWM1__FUNC_PWM1 (MTK_PIN_NO(128) | 1) +#define MT6572_PIN_128_PWM1__FUNC_EINT2 (MTK_PIN_NO(128) | 2) +#define MT6572_PIN_128_PWM1__FUNC_UCTS1 (MTK_PIN_NO(128) | 3) +#define MT6572_PIN_128_PWM1__FUNC_SRCLKENAI (MTK_PIN_NO(128) | 4) +#define MT6572_PIN_128_PWM1__FUNC_MD_CLKM0 (MTK_PIN_NO(128) | 5) +#define MT6572_PIN_128_PWM1__FUNC_LSCK (MTK_PIN_NO(128) | 6) +#define MT6572_PIN_128_PWM1__FUNC_CONN_GPIO30 (MTK_PIN_NO(128) | 7) + +#define MT6572_PIN_129_PWM2__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT6572_PIN_129_PWM2__FUNC_PWM2 (MTK_PIN_NO(129) | 1) +#define MT6572_PIN_129_PWM2__FUNC_EINT1 (MTK_PIN_NO(129) | 2) +#define MT6572_PIN_129_PWM2__FUNC_URTS1 (MTK_PIN_NO(129) | 3) +#define MT6572_PIN_129_PWM2__FUNC_USB_IDDIG (MTK_PIN_NO(129) | 4) +#define MT6572_PIN_129_PWM2__FUNC_MD_CLKM1 (MTK_PIN_NO(129) | 5) +#define MT6572_PIN_129_PWM2__FUNC_LSDA (MTK_PIN_NO(129) | 6) +#define MT6572_PIN_129_PWM2__FUNC_CONN_GPIO31 (MTK_PIN_NO(129) | 7) + +#define MT6572_PIN_130_BPI_BUS0__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT6572_PIN_130_BPI_BUS0__FUNC_BPI_BUS0 (MTK_PIN_NO(130) | 1) +#define MT6572_PIN_130_BPI_BUS0__FUNC_DBG_OUT0 (MTK_PIN_NO(130) | 6) +#define MT6572_PIN_130_BPI_BUS0__FUNC_CONN_GPIO0 (MTK_PIN_NO(130) | 7) + +#define MT6572_PIN_131_BPI_BUS1__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT6572_PIN_131_BPI_BUS1__FUNC_BPI_BUS1 (MTK_PIN_NO(131) | 1) +#define MT6572_PIN_131_BPI_BUS1__FUNC_DBG_OUT1 (MTK_PIN_NO(131) | 6) +#define MT6572_PIN_131_BPI_BUS1__FUNC_CONN_GPIO1 (MTK_PIN_NO(131) | 7) + +#define MT6572_PIN_132_BPI_BUS2__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT6572_PIN_132_BPI_BUS2__FUNC_BPI_BUS2 (MTK_PIN_NO(132) | 1) +#define MT6572_PIN_132_BPI_BUS2__FUNC_DBG_OUT2 (MTK_PIN_NO(132) | 6) +#define MT6572_PIN_132_BPI_BUS2__FUNC_CONN_GPIO2 (MTK_PIN_NO(132) | 7) + +#define MT6572_PIN_133_BPI_BUS3__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT6572_PIN_133_BPI_BUS3__FUNC_BPI_BUS3 (MTK_PIN_NO(133) | 1) +#define MT6572_PIN_133_BPI_BUS3__FUNC_DBG_OUT3 (MTK_PIN_NO(133) | 6) +#define MT6572_PIN_133_BPI_BUS3__FUNC_CONN_GPIO3 (MTK_PIN_NO(133) | 7) + +#define MT6572_PIN_134_BPI_BUS4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT6572_PIN_134_BPI_BUS4__FUNC_BPI_BUS4 (MTK_PIN_NO(134) | 1) +#define MT6572_PIN_134_BPI_BUS4__FUNC_ANT_SEL0 (MTK_PIN_NO(134) | 2) +#define MT6572_PIN_134_BPI_BUS4__FUNC_PWM2 (MTK_PIN_NO(134) | 4) +#define MT6572_PIN_134_BPI_BUS4__FUNC_I2S_OUT_WS (MTK_PIN_NO(134) | 5) +#define MT6572_PIN_134_BPI_BUS4__FUNC_DBG_OUT4 (MTK_PIN_NO(134) | 6) +#define MT6572_PIN_134_BPI_BUS4__FUNC_CONN_GPIO4 (MTK_PIN_NO(134) | 7) + +#define MT6572_PIN_135_BPI_BUS5__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT6572_PIN_135_BPI_BUS5__FUNC_BPI_BUS5 (MTK_PIN_NO(135) | 1) +#define MT6572_PIN_135_BPI_BUS5__FUNC_ANT_SEL1 (MTK_PIN_NO(135) | 2) +#define MT6572_PIN_135_BPI_BUS5__FUNC_EINT0 (MTK_PIN_NO(135) | 4) +#define MT6572_PIN_135_BPI_BUS5__FUNC_I2S_OUT_CK (MTK_PIN_NO(135) | 5) +#define MT6572_PIN_135_BPI_BUS5__FUNC_DBG_OUT5 (MTK_PIN_NO(135) | 6) +#define MT6572_PIN_135_BPI_BUS5__FUNC_CONN_GPIO5 (MTK_PIN_NO(135) | 7) + +#define MT6572_PIN_136_BPI_BUS6__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT6572_PIN_136_BPI_BUS6__FUNC_BPI_BUS6 (MTK_PIN_NO(136) | 1) +#define MT6572_PIN_136_BPI_BUS6__FUNC_ANT_SEL2 (MTK_PIN_NO(136) | 2) +#define MT6572_PIN_136_BPI_BUS6__FUNC_SFCS2_MX (MTK_PIN_NO(136) | 3) +#define MT6572_PIN_136_BPI_BUS6__FUNC_EINT2 (MTK_PIN_NO(136) | 4) +#define MT6572_PIN_136_BPI_BUS6__FUNC_I2S_OUT_DAT (MTK_PIN_NO(136) | 5) +#define MT6572_PIN_136_BPI_BUS6__FUNC_DBG_OUT6 (MTK_PIN_NO(136) | 6) +#define MT6572_PIN_136_BPI_BUS6__FUNC_CONN_GPIO6 (MTK_PIN_NO(136) | 7) + +#define MT6572_PIN_137_BPI_BUS7__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT6572_PIN_137_BPI_BUS7__FUNC_BPI_BUS7 (MTK_PIN_NO(137) | 1) +#define MT6572_PIN_137_BPI_BUS7__FUNC_BSI2_DATA (MTK_PIN_NO(137) | 2) +#define MT6572_PIN_137_BPI_BUS7__FUNC_SCL_1_3 (MTK_PIN_NO(137) | 3) +#define MT6572_PIN_137_BPI_BUS7__FUNC_DBG_OUT7 (MTK_PIN_NO(137) | 6) +#define MT6572_PIN_137_BPI_BUS7__FUNC_CONN_GPIO7 (MTK_PIN_NO(137) | 7) + +#define MT6572_PIN_138_BPI_BUS8__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT6572_PIN_138_BPI_BUS8__FUNC_BPI_BUS8 (MTK_PIN_NO(138) | 1) +#define MT6572_PIN_138_BPI_BUS8__FUNC_BSI2_CLK (MTK_PIN_NO(138) | 2) +#define MT6572_PIN_138_BPI_BUS8__FUNC_SDA_1_3 (MTK_PIN_NO(138) | 3) +#define MT6572_PIN_138_BPI_BUS8__FUNC_DBG_OUT8 (MTK_PIN_NO(138) | 6) +#define MT6572_PIN_138_BPI_BUS8__FUNC_CONN_GPIO8 (MTK_PIN_NO(138) | 7) + +#define MT6572_PIN_139_BPI_BUS9__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT6572_PIN_139_BPI_BUS9__FUNC_BPI_BUS9 (MTK_PIN_NO(139) | 1) +#define MT6572_PIN_139_BPI_BUS9__FUNC_USB_DRVVBUS (MTK_PIN_NO(139) | 4) +#define MT6572_PIN_139_BPI_BUS9__FUNC_DBG_OUT9 (MTK_PIN_NO(139) | 6) +#define MT6572_PIN_139_BPI_BUS9__FUNC_CONN_GPIO9 (MTK_PIN_NO(139) | 7) + +#define MT6572_PIN_140_BPI_BUS10__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT6572_PIN_140_BPI_BUS10__FUNC_BPI_BUS10 (MTK_PIN_NO(140) | 1) +#define MT6572_PIN_140_BPI_BUS10__FUNC_EINT6 (MTK_PIN_NO(140) | 4) +#define MT6572_PIN_140_BPI_BUS10__FUNC_DBG_OUT10 (MTK_PIN_NO(140) | 6) +#define MT6572_PIN_140_BPI_BUS10__FUNC_CONN_GPIO10 (MTK_PIN_NO(140) | 7) + +#define MT6572_PIN_141_BPI_BUS11__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT6572_PIN_141_BPI_BUS11__FUNC_BPI_BUS11 (MTK_PIN_NO(141) | 1) +#define MT6572_PIN_141_BPI_BUS11__FUNC_DBG_OUT11 (MTK_PIN_NO(141) | 6) +#define MT6572_PIN_141_BPI_BUS11__FUNC_CONN_GPIO11 (MTK_PIN_NO(141) | 7) + +#define MT6572_PIN_142_BPI_BUS12__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT6572_PIN_142_BPI_BUS12__FUNC_BPI_BUS12 (MTK_PIN_NO(142) | 1) +#define MT6572_PIN_142_BPI_BUS12__FUNC_LSA0 (MTK_PIN_NO(142) | 2) +#define MT6572_PIN_142_BPI_BUS12__FUNC_EINT7 (MTK_PIN_NO(142) | 3) +#define MT6572_PIN_142_BPI_BUS12__FUNC_I2S_IN_WS (MTK_PIN_NO(142) | 4) +#define MT6572_PIN_142_BPI_BUS12__FUNC_KROW3 (MTK_PIN_NO(142) | 5) +#define MT6572_PIN_142_BPI_BUS12__FUNC_DBG_OUT12 (MTK_PIN_NO(142) | 6) +#define MT6572_PIN_142_BPI_BUS12__FUNC_CONN_GPIO12 (MTK_PIN_NO(142) | 7) + +#define MT6572_PIN_143_BPI_BUS13__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT6572_PIN_143_BPI_BUS13__FUNC_BPI_BUS13 (MTK_PIN_NO(143) | 1) +#define MT6572_PIN_143_BPI_BUS13__FUNC_PWM1 (MTK_PIN_NO(143) | 2) +#define MT6572_PIN_143_BPI_BUS13__FUNC_EINT4 (MTK_PIN_NO(143) | 3) +#define MT6572_PIN_143_BPI_BUS13__FUNC_I2S_IN_CK (MTK_PIN_NO(143) | 4) +#define MT6572_PIN_143_BPI_BUS13__FUNC_KROW4 (MTK_PIN_NO(143) | 5) +#define MT6572_PIN_143_BPI_BUS13__FUNC_DBG_OUT13 (MTK_PIN_NO(143) | 6) +#define MT6572_PIN_143_BPI_BUS13__FUNC_CONN_GPIO13 (MTK_PIN_NO(143) | 7) + +#define MT6572_PIN_144_BPI_BUS14__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT6572_PIN_144_BPI_BUS14__FUNC_BPI_BUS14 (MTK_PIN_NO(144) | 1) +#define MT6572_PIN_144_BPI_BUS14__FUNC_PWM2 (MTK_PIN_NO(144) | 2) +#define MT6572_PIN_144_BPI_BUS14__FUNC_EINT5 (MTK_PIN_NO(144) | 3) +#define MT6572_PIN_144_BPI_BUS14__FUNC_I2S_IN_DAT (MTK_PIN_NO(144) | 4) +#define MT6572_PIN_144_BPI_BUS14__FUNC_KROW5 (MTK_PIN_NO(144) | 5) +#define MT6572_PIN_144_BPI_BUS14__FUNC_DBG_OUT14 (MTK_PIN_NO(144) | 6) +#define MT6572_PIN_144_BPI_BUS14__FUNC_CONN_GPIO14 (MTK_PIN_NO(144) | 7) + +#define MT6572_PIN_145_BPI_BUS15__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT6572_PIN_145_BPI_BUS15__FUNC_BPI_BUS15 (MTK_PIN_NO(145) | 1) +#define MT6572_PIN_145_BPI_BUS15__FUNC_PWM_BL (MTK_PIN_NO(145) | 2) +#define MT6572_PIN_145_BPI_BUS15__FUNC_EINT8 (MTK_PIN_NO(145) | 3) +#define MT6572_PIN_145_BPI_BUS15__FUNC_LSDI (MTK_PIN_NO(145) | 4) +#define MT6572_PIN_145_BPI_BUS15__FUNC_KROW6 (MTK_PIN_NO(145) | 5) +#define MT6572_PIN_145_BPI_BUS15__FUNC_DBG_OUT15 (MTK_PIN_NO(145) | 6) +#define MT6572_PIN_145_BPI_BUS15__FUNC_CONN_GPIO15 (MTK_PIN_NO(145) | 7) + +#define MT6572_PIN_146_TXBPI__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT6572_PIN_146_TXBPI__FUNC_TXBPI (MTK_PIN_NO(146) | 1) + +#define MT6572_PIN_147_VM0__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT6572_PIN_147_VM0__FUNC_VM0 (MTK_PIN_NO(147) | 1) + +#define MT6572_PIN_148_VM1__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT6572_PIN_148_VM1__FUNC_VM1 (MTK_PIN_NO(148) | 1) + +#define MT6572_PIN_149_BSI_EN__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT6572_PIN_149_BSI_EN__FUNC_BSI_EN (MTK_PIN_NO(149) | 1) + +#define MT6572_PIN_150_BSI_CLK__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT6572_PIN_150_BSI_CLK__FUNC_BSI_CLK (MTK_PIN_NO(150) | 1) + +#define MT6572_PIN_151_BSI_DATA0__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT6572_PIN_151_BSI_DATA0__FUNC_BSI_DATA0 (MTK_PIN_NO(151) | 1) + +#define MT6572_PIN_152_BSI_DATA1__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT6572_PIN_152_BSI_DATA1__FUNC_BSI_DATA1 (MTK_PIN_NO(152) | 1) + +#define MT6572_PIN_153_BSI_DATA2__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT6572_PIN_153_BSI_DATA2__FUNC_BSI_DATA2 (MTK_PIN_NO(153) | 1) + +#endif From 5fc29eaaab337bdc1843f44b7624609074a7757b Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:19:20 +0200 Subject: [PATCH 04/69] dt-bindings: memory: add mt6572 Add a header for the IOMMU ports on the mt6572 SoC. Signed-off-by: rva3 --- include/dt-bindings/memory/mt6572-larb-port.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 include/dt-bindings/memory/mt6572-larb-port.h diff --git a/include/dt-bindings/memory/mt6572-larb-port.h b/include/dt-bindings/memory/mt6572-larb-port.h new file mode 100644 index 00000000000000..335a5b6bd76a97 --- /dev/null +++ b/include/dt-bindings/memory/mt6572-larb-port.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2026 rva3 + */ + +#ifndef _DT_BINDINGS_MEMORY_MT6572_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6572_LARB_PORT_H_ + +#define MT6572_M4U_PORT_DISP_OVL 0 +#define MT6572_M4U_PORT_LCD_R 1 +#define MT6572_M4U_PORT_LCD_W 2 +#define MT6572_M4U_PORT_LCD_DBI 3 +#define MT6572_M4U_PORT_CAM_WDMA 4 +#define MT6572_M4U_PORT_CMDQ 5 +#define MT6572_M4U_PORT_VENC_BSDMA_VDEC_POST 5 +#define MT6572_M4U_PORT_MDP_RDMA 7 +#define MT6572_M4U_PORT_MDP_WDMA 8 +#define MT6572_M4U_PORT_MDP_ROTO 9 +#define MT6572_M4U_PORT_MDP_ROTCO 10 +#define MT6572_M4U_PORT_MDP_ROTVO 11 + +#endif From 7537ba0d9315d09051aedcb4dcb36753b442ec6f Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:35:40 +0200 Subject: [PATCH 05/69] dt-bindings: power: add mt6572 Add a header for the power domains on the mt6572 SoC. Signed-off-by: rva3 --- .../power/mediatek,mt6572-power-controller.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt6572-power-controller.h diff --git a/include/dt-bindings/power/mediatek,mt6572-power-controller.h b/include/dt-bindings/power/mediatek,mt6572-power-controller.h new file mode 100644 index 00000000000000..b235f2a45a6a5f --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt6572-power-controller.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_MT6572_POWER_CONTROLLER_H +#define _DT_BINDINGS_POWER_MT6572_POWER_CONTROLLER_H + +//#define MT6572_POWER_DOMAIN_MD1 0 +//#define MT6572_POWER_DOMAIN_CONN 1 +#define MT6572_POWER_DOMAIN_DPY 2 +#define MT6572_POWER_DOMAIN_DIS 1 +#define MT6572_POWER_DOMAIN_MFG 0 +#define MT6572_POWER_DOMAIN_ISP 5 +#define MT6572_POWER_DOMAIN_IFR 6 +#define MT6572_POWER_DOMAIN_VDE 7 +#define MT6572_POWER_DOMAIN_VEN 8 + +#endif From 6cc923cf0d79e1df510979cc292a287ccdb4bd22 Mon Sep 17 00:00:00 2001 From: Custom Firmware Date: Thu, 21 May 2026 23:54:21 +0300 Subject: [PATCH 06/69] dt-bindings: i2c: mt65xx: document mt6572 separate RX DMA channel mt6572's I2C controllers have two physically separate APDMA channel register blocks per bus: TX at the DMA base address declared in the SoC DTSI's second reg entry, and RX at a different address that the driver previously assumed was reachable at a fixed offset from TX. Add mediatek,mt6572-i2c to the compatible enum, document the third reg entry for the RX DMA channel, and conditionally require exactly three reg entries when the compatible is mediatek,mt6572-i2c (every other SoC still requires two). The driver-side support for the third reg entry lands in a follow-up patch. Signed-off-by: Custom Firmware --- .../devicetree/bindings/i2c/i2c-mt65xx.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index ecd5783f001b3e..b10311e72af168 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -12,6 +12,20 @@ description: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt6572-i2c + then: + properties: + reg: + minItems: 3 + maxItems: 3 + else: + properties: + reg: + maxItems: 2 maintainers: - Qii Wang @@ -20,6 +34,7 @@ properties: compatible: oneOf: - const: mediatek,mt2712-i2c + - const: mediatek,mt6572-i2c - const: mediatek,mt6577-i2c - const: mediatek,mt6589-i2c - const: mediatek,mt7622-i2c @@ -64,9 +79,11 @@ properties: - const: mediatek,mt8192-i2c reg: + minItems: 2 items: - description: Physical base address - - description: DMA base address + - description: DMA base address (TX channel on mt6572) + - description: DMA RX channel base address (mt6572 only) interrupts: maxItems: 1 From b568b59599c5f9977095dba6b0de52c444713c39 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:18:42 +0200 Subject: [PATCH 07/69] watchdog: mtk: add mt6572 support Add support for the watchdog reset controller on the mt6572 SoC. Signed-off-by: rva3 --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 91d110646e16f7..7b5668fee3785b 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -88,6 +89,10 @@ static const struct mtk_wdt_data mt2712_data = { .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt6572_data = { + .toprgu_sw_rst_num = MT6572_TOPRGU_SW_RST_NUM, +}; + static const struct mtk_wdt_data mt6735_data = { .toprgu_sw_rst_num = MT6735_TOPRGU_RST_NUM, }; @@ -493,6 +498,7 @@ static int mtk_wdt_resume(struct device *dev) static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, + { .compatible = "mediatek,mt6572-wdt", .data = &mt6572_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data }, { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, From 886161da1f849973183c87c62dae5b17d3c57aaf Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:21:48 +0200 Subject: [PATCH 08/69] clk: mediatek: add mt6572 clocks support XXX: probably unsquash Signed-off-by: rva3 --- drivers/clk/mediatek/Kconfig | 8 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6572-apmixedsys.c | 137 +++++++ drivers/clk/mediatek/clk-mt6572-infracfg.c | 47 +++ drivers/clk/mediatek/clk-mt6572-mfg.c | 52 +++ drivers/clk/mediatek/clk-mt6572-mm.c | 82 ++++ drivers/clk/mediatek/clk-mt6572-topckgen.c | 384 ++++++++++++++++++ .../dt-bindings/clock/mediatek,mt6572-clk.h | 172 +++++--- 8 files changed, 829 insertions(+), 54 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt6572-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt6572-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt6572-mfg.c create mode 100644 drivers/clk/mediatek/clk-mt6572-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6572-topckgen.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 2c09fd729bab04..4046053284b743 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,14 @@ config COMMON_CLK_MT2712_VENCSYS help This driver supports MediaTek MT2712 vencsys clocks. +config COMMON_CLK_MT6572 + bool "Clock driver for MediaTek MT6572" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM + help + This driver supports MediaTek MT6572 basic clocks. + config COMMON_CLK_MT6735 tristate "Main clock drivers for MediaTek MT6735" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index d8736a060dbdca..dbf0f07c043a33 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o +obj-$(CONFIG_COMMON_CLK_MT6572) += clk-mt6572-topckgen.o clk-mt6572-apmixedsys.o clk-mt6572-infracfg.o clk-mt6572-mm.o clk-mt6572-mfg.o obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o diff --git a/drivers/clk/mediatek/clk-mt6572-apmixedsys.c b/drivers/clk/mediatek/clk-mt6572-apmixedsys.c new file mode 100644 index 00000000000000..88d3d8d6c00c12 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6572-apmixedsys.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "clk-mux.h" +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#include + +#define ARMPLL_OFFSET 0x100 +#define MAINPLL_OFFSET 0x120 +#define UNIVPLL_OFFSET 0x140 +#define WHPLL_OFFSET 0x240 + +#define WHPLL_PATHSEL_CON 0x254 +#define RSV_RW0_CON1 0xf04 + +#define REG_CON0 0x0 +#define REG_CON1 0x4 +#define REG_PWR_CON0 0x10 + +#define CON0_RST_BAR BIT(27) + +#define PLL_DIV(_id, _name, _base, _en_mask, _rst_bar_mask, _flags, _fmin, \ + _fmax, _div) \ + { .id = _id, \ + .name = _name, \ + .parent_name = "clk26m", \ + .reg = (_base) + REG_CON0, \ + .pwr_reg = (_base) + REG_PWR_CON0, \ + .en_mask = _en_mask, \ + .rst_bar_mask = _rst_bar_mask, \ + .pd_reg = (_base) + REG_CON1, \ + .pd_shift = 24, \ + .pcw_reg = (_base) + REG_CON1, \ + .pcw_chg_reg = (_base) + REG_CON1, \ + .pcwbits = 21, \ + .flags = _flags, \ + .fmin = _fmin, \ + .fmax = _fmax, \ + .div_table = _div } + +#define PLL_FREQ(_id, _name, _base, _en_mask, _rst_bar_mask, _flags, _fmin, _fmax) \ + PLL_DIV(_id, _name, _base, _en_mask, _rst_bar_mask, _flags, _fmin, _fmax, NULL) + +#define PLL(_id, _name, _base, _en_mask, _rst_bar_mask, _flags) \ + PLL_DIV(_id, _name, _base, _en_mask, _rst_bar_mask, _flags, 0, 0, NULL) + +static const struct mtk_pll_div_table armpll_div_table[] = { + { .div = 0, .freq = 1989 * MHZ }, + { .div = 1, .freq = 1001 * MHZ }, + { .div = 2, .freq = 520 * MHZ }, + { .div = 3, .freq = 260 * MHZ }, + { .div = 4, .freq = 130 * MHZ }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data apmixedsys_plls[] = { + PLL_DIV(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_OFFSET, 0x00000011, 0, + PLL_AO, 1000 * MHZ, 1800 * MHZ, armpll_div_table), + + PLL_FREQ(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_OFFSET, 0x00000011, + CON0_RST_BAR, PLL_AO | HAVE_RST_BAR, 1000 * MHZ, 1800 * MHZ), + + //PLL_FREQ(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_OFFSET, 0x30000011, + // CON0_RST_BAR, HAVE_RST_BAR, 1248 * MHZ, 1248 * MHZ), + + PLL_DIV(CLK_APMIXED_WHPLL, "whpll", WHPLL_OFFSET, 0x00000011, 0, 0, + 754 * MHZ, 1508 * MHZ, armpll_div_table), +}; + +static int clk_mt6572_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk_hw_onecell_data *clk_data; + int ret; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* + * WHPLL requires WHPLL_PATHSEL_CON and RSV_RW0_CON1 setup to enable + * output. Otherwise the GPU will get 0 Hz and hang. + */ + writel(1, base + WHPLL_PATHSEL_CON); + writel(0xC0000000, base + RSV_RW0_CON1); + + clk_data = mtk_devm_alloc_clk_data(&pdev->dev, ARRAY_SIZE(apmixedsys_plls)); + if (!clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, clk_data); + + ret = mtk_clk_register_plls(&pdev->dev, apmixedsys_plls, + ARRAY_SIZE(apmixedsys_plls), clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret); + return ret; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + clk_data); + if (ret) + dev_err(&pdev->dev, + "Failed to register clock provider: %d\n", ret); + + return ret; +} + +static void clk_mt6572_apmixed_remove(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data); +} + +static const struct of_device_id of_match_mt6572_apmixedsys[] = { + { .compatible = "mediatek,mt6572-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_mt6572_apmixedsys); + +static struct platform_driver clk_mt6572_apmixedsys = { + .probe = clk_mt6572_apmixed_probe, + .remove = clk_mt6572_apmixed_remove, + .driver = { + .name = "clk-mt6572-apmixedsys", + .of_match_table = of_match_mt6572_apmixedsys, + }, +}; +module_platform_driver(clk_mt6572_apmixedsys); + +MODULE_DESCRIPTION("MediaTek MT6572 apmixedsys clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6572-infracfg.c b/drivers/clk/mediatek/clk-mt6572-infracfg.c new file mode 100644 index 00000000000000..1a92294871c36f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6572-infracfg.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026 rva3 + */ + +#include +#include + +#include "clk-mtk.h" + +#include + +static const char * const cpu_mux_parents[] = { + "clk26m", + "armpll", + "univpll", + "mpll_d2" +}; + +static const struct mtk_composite infra_muxes[] = { + MUX(CLK_INFRA_CPUSEL, "cpu_mux", cpu_mux_parents, 0x0, 2, 2), +}; + +static const struct mtk_clk_desc infracfg_clks = { + .composite_clks = infra_muxes, + .num_composite_clks = ARRAY_SIZE(infra_muxes), +}; + +static const struct of_device_id of_match_mt6572_infracfg[] = { + { .compatible = "mediatek,mt6572-infracfg", .data = &infracfg_clks }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_mt6572_infracfg); + +static struct platform_driver clk_mt6572_infracfg = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6572-infracfg", + .of_match_table = of_match_mt6572_infracfg, + }, +}; +module_platform_driver(clk_mt6572_infracfg); + +MODULE_DESCRIPTION("MediaTek MT6572 infracfg clock driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/clk/mediatek/clk-mt6572-mfg.c b/drivers/clk/mediatek/clk-mt6572-mfg.c new file mode 100644 index 00000000000000..75fed991fc4983 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6572-mfg.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mfg_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mfg_clks[] = { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), +}; + +static const struct mtk_clk_desc mfg_desc = { + .clks = mfg_clks, + .num_clks = ARRAY_SIZE(mfg_clks), +}; + +static const struct of_device_id of_match_clk_mt6572_mfg[] = { + { + .compatible = "mediatek,mt6572-mfgcfg", + .data = &mfg_desc, + }, + { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6572_mfg); + +static struct platform_driver clk_mt6572_mfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6572-mfg", + .of_match_table = of_match_clk_mt6572_mfg, + }, +}; +module_platform_driver(clk_mt6572_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT6572 GPU mfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6572-mm.c b/drivers/clk/mediatek/clk-mt6572-mm.c new file mode 100644 index 00000000000000..58e15dc80672cc --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6572-mm.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mm0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mm1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr) + +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr) + + +static const struct mtk_gate mm_clks[] = { + GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_smi_src", 0), + GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_smi_src", 1), + GATE_MM0(CLK_MM_CMDQ, "mm_cmdq", "mm_smi_src", 2), + GATE_MM0(CLK_MM_SMI_CMDQ, "mm_smi_cmdq", "mm_smi_src", 3), + GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_smi_src", 4), + GATE_MM0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_smi_src", 5), + GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_smi_src", 6), + GATE_MM0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_smi_src", 7), + GATE_MM0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_smi_src", 8), + GATE_MM0(CLK_MM_DISP_MDP_TDSHP, "mm_mdp_tdshp", "mm_smi_src", 9), + GATE_MM0(CLK_MM_DISP_MDP_WROT, "mm_mdp_wrot", "mm_smi_src", 10), + GATE_MM0(CLK_MM_DISP_MDP_WDMA, "mm_mdp_wdma", "mm_smi_src", 11), + GATE_MM0(CLK_MM_DISP_MDP_RSZ1, "mm_mdp_rsz1", "mm_smi_src", 12), + GATE_MM0(CLK_MM_DISP_MDP_RSZ0, "mm_mdp_rsz0", "mm_smi_src", 13), + GATE_MM0(CLK_MM_DISP_MDP_RDMA, "mm_mdp_rdma", "mm_smi_src", 14), + GATE_MM0(CLK_MM_DISP_MDP_BLS_26M, "mm_mdp_bls_26m", "mm_smi_src", 15), + GATE_MM0(CLK_MM_CAM, "mm_cam", "mm_smi_src", 16), + GATE_MM0(CLK_MM_SENINF, "mm_seninf", "mm_smi_src", 17), + GATE_MM0(CLK_MM_CAMTG, "mm_camtg", "mm_smi_src", 18), + GATE_MM0(CLK_MM_CODEC, "mm_codec", "mm_smi_src", 19), + GATE_MM0(CLK_MM_DISP_FAKE_ENG, "mm_disp_fake_eng", "mm_smi_src", 20), + GATE_MM0(CLK_MM_MUTEX_SLOW_CLOCK, "mm_mutex_slow_clock", "mm_smi_src", 21), + + GATE_MM1(CLK_MM_DSI_ENGINE, "dsi_engine", "mm_smi_src", 0), + GATE_MM1(CLK_MM_DSI_DIGITAL, "dsi_digital", "mm_smi_src", 1), +}; + +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; + +static const struct platform_device_id clk_mt6572_mm_id_table[] = { + { .name = "clk-mt6572-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt6572_mm_id_table); + +static struct platform_driver clk_mt6572_mm = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, + .driver = { + .name = "clk-mt6572-mm", + }, + .id_table = clk_mt6572_mm_id_table, +}; +module_platform_driver(clk_mt6572_mm); + +MODULE_DESCRIPTION("MediaTek MT6572 MultiMedia clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6572-topckgen.c b/drivers/clk/mediatek/clk-mt6572-topckgen.c new file mode 100644 index 00000000000000..61fecf53416d0f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6572-topckgen.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "clk-gate.h" +#include +#include + +#include "clk-mtk.h" + +#include + +#define CLK_CFG_0 0x00 +#define CLK_CFG_0_SET 0x04 +#define CLK_CFG_0_CLR 0x08 + +static DEFINE_SPINLOCK(mt6572_topckgen_lock); + +static const struct mtk_fixed_clk topckgen_fixed_clks[] = { + FIXED_CLK(CLK_TOP_SC_26M_SEL, "sc_26m_sel", "clk26m", 26 * MHZ), +}; + +static const struct mtk_fixed_factor topckgen_factors[] = { + FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mainpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D3, "mpll_d3", "mainpll", 1, 3), + FACTOR(CLK_TOP_MPLL_D5, "mpll_d5", "mainpll", 1, 5), + FACTOR(CLK_TOP_MPLL_D7, "mpll_d7", "mainpll", 1, 7), + FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mainpll", 1, 4), + FACTOR(CLK_TOP_MPLL_D6, "mpll_d6", "mainpll", 1, 6), + FACTOR(CLK_TOP_MPLL_D10, "mpll_d10", "mainpll", 1, 10), + FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mainpll", 1, 8), + FACTOR(CLK_TOP_MPLL_D12, "mpll_d12", "mainpll", 1, 12), + FACTOR(CLK_TOP_MPLL_D20, "mpll_d20", "mainpll", 1, 20), + FACTOR(CLK_TOP_MPLL_D24, "mpll_d24", "mainpll", 1, 24), + + FACTOR(CLK_TOP_UPLL_D2, "upll_d2", "univpll", 1, 2), + FACTOR(CLK_TOP_UPLL_D3, "upll_d3", "univpll", 1, 3), + FACTOR(CLK_TOP_UPLL_D5, "upll_d5", "univpll", 1, 5), + FACTOR(CLK_TOP_UPLL_D7, "upll_d7", "univpll", 1, 7), + FACTOR(CLK_TOP_UPLL_D4, "upll_d4", "univpll", 1, 4), + FACTOR(CLK_TOP_UPLL_D6, "upll_d6", "univpll", 1, 6), + FACTOR(CLK_TOP_UPLL_D10, "upll_d10", "univpll", 1, 10), + FACTOR(CLK_TOP_UPLL_D8, "upll_d8", "univpll", 1, 8), + FACTOR(CLK_TOP_UPLL_D12, "upll_d12", "univpll", 1, 12), + FACTOR(CLK_TOP_UPLL_D20, "upll_d20", "univpll", 1, 20), + FACTOR(CLK_TOP_UPLL_D16, "upll_d16", "univpll", 1, 16), + FACTOR(CLK_TOP_UPLL_D24, "upll_d24", "univpll", 1, 24), + + FACTOR(CLK_TOP_UNIV_48M_SEL, "univ_48m", "univpll", 1, 26), +}; + +static const char * const uart_sel_parents[] = { + "clk26m", + "upll_d24" +}; + +static const char * const emi2x_sel_parents[] = { + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "mpll_d3", + "mpll_d4", + "clk26m", + "mpll_d2" +}; + +static const char * const axi_sel_parents[] = { + "clk26m", + "clk26m", + "mpll_d10", + "clk26m", + "mpll_d12" +}; + +static const char *const mfg_mux_parents[] = { + "mfg_pre_491m", // 3'b000: 491.52 MHz + "mfg_pre_500m", // 3'b001: 500.5 MHz (whpll) + "mpll_d3", // 3'b010: "mainpll output clock divided by 3 (designed for DDR 533MHz case)" from datasheet suggests this one should be mpll_d3, and previous one is some fixed clock? mainpll rate depends on the DRAM type... + "upll_d2", // 3'b011: 624 MHz (upll is 1248 MHz) + "clk26m", // 3'b1x0: 26 MHz + "mpll_d2", // 3'b1x1: "mainpll output clock divided by 2 (designed for DDR 663MHz case)" from datasheet suggests this one should be mpll_d2, and previous one is some fixed clock? mainpll rate depends on the DRAM type... + "clk26m", // 3'b1x0: 26 MHz + "mpll_d2", // 3'b1x1: "mainpll output clock divided by 2 (designed for DDR 663MHz case)" from datasheet suggests this one should be mpll_d2, and previous one is some fixed clock? mainpll rate depends on the DRAM type... +}; + +static const char *const mfg_gf_parents[] = { + "upll_d3", // 0 = 416 MHz + "mfg_mux_sel" // 1 = the mux +}; + +static const char * const msdc0_sel_parents[] = { + "mpll_d12", + "mpll_d10", + "mpll_d8", + "upll_d7", + "mpll_d7", + "mpll_d8", + "clk26m", + "upll_d6" +}; + +static const char * const spi_nand_sel_parents[] = { + "mpll_d24", + "mpll_d20", + "upll_d20", + "upll_d16", + "upll_d12", + "upll_d10", + "mpll_d12", + "mpll_d10", +}; + +static const char * const cam_sel_parents[] = { + "univ_48m", + "upll_d6" +}; + +static const char * const pwm_mm_sel_parents[] = { + "clk26m", + "upll_d12" +}; + +static const char * const msdc1_sel_parents[] = { + "mpll_d12", + "mpll_d10", + "mpll_d8", + "upll_d7", + "mpll_d7", + "mpll_d8", + "clk26m", + "upll_d6" +}; + +static const char * const spm_52m_sel_parents[] = { + "clk26m", + "upll_d24" +}; + +static const char * const pmic_spi_sel_ddr2_parents[] = { + "mpll_d24", + "univ_48m", + "upll_d16", + "clk26m" +}; + +static const char * const pmic_spi_sel_ddr3_parents[] = { + "mpll_d20", + "univ_48m", + "upll_d16", + "clk26m" +}; + +static const char * const audio_intbus_sel_ddr2_parents[] = { + "clk26m", + "clk26m", + "mpll_d24", + "clk26m", + "mpll_d12" +}; + +static const char * const audio_intbus_sel_ddr3_parents[] = { + "clk26m", + "clk26m", + "mpll_d20", + "clk26m", + "mpll_d10" +}; + +static const char * const spinfi_pre_sel_parents[] = { + "clk26m", + "spinfi_sel" +}; + +static const struct mtk_composite topckgen_ddr2_muxes[] = { + MUX(CLK_TOP_PMIC_SPI_SEL, "pmic_spi_sel", pmic_spi_sel_ddr2_parents, CLK_CFG_0, 24, 2), + MUX(CLK_TOP_AUDIO_INTBUS_SEL, "audio_intbus_sel", audio_intbus_sel_ddr2_parents, CLK_CFG_0, 27, 3), +}; + +static const struct mtk_composite topckgen_ddr3_muxes[] = { + MUX(CLK_TOP_PMIC_SPI_SEL, "pmic_spi_sel", pmic_spi_sel_ddr3_parents, CLK_CFG_0, 24, 2), + MUX(CLK_TOP_AUDIO_INTBUS_SEL, "audio_intbus_sel", audio_intbus_sel_ddr3_parents, CLK_CFG_0, 27, 3), +}; + +static const struct mtk_composite topckgen_muxes[] = { + MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart_sel_parents, CLK_CFG_0, 0, 1), + MUX_FLAGS(CLK_TOP_EMI2X_SEL, "emi2x_sel", emi2x_sel_parents, CLK_CFG_0, + 1, 4, CLK_IS_CRITICAL), + MUX_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, 5, 3, + CLK_IS_CRITICAL), + MUX_FLAGS(CLK_TOP_MFG_MUX_SEL, "mfg_mux_sel", mfg_mux_parents, CLK_CFG_0, + 8, 3, CLK_SET_RATE_PARENT), + MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_sel_parents, CLK_CFG_0, 11, + 3), + MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spi_nand_sel_parents, CLK_CFG_0, + 14, 3), + MUX(CLK_TOP_CAM_SEL, "cam_sel", cam_sel_parents, CLK_CFG_0, 17, 1), + MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_sel_parents, CLK_CFG_0, 18, + 1), + MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart_sel_parents, CLK_CFG_0, 19, 1), + MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_sel_parents, CLK_CFG_0, 20, + 3), + MUX_FLAGS(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_sel_parents, + CLK_CFG_0, 23, 1, CLK_IS_CRITICAL), + MUX(CLK_TOP_SPINFI_PRE_SEL, "spinfi_pre_sel", spinfi_pre_sel_parents, + CLK_CFG_0, 30, 1), + MUX_FLAGS(CLK_TOP_MFG_SEL, "mfg_sel", mfg_gf_parents, CLK_CFG_0, 31, 1, + CLK_SET_RATE_PARENT), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .sta_ofs = 0x20, + .set_ofs = 0x50, + .clr_ofs = 0x80, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .sta_ofs = 0x24, + .set_ofs = 0x54, + .clr_ofs = 0x84, +}; + +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP0_INV(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate top_ddr2_clks[] = { + GATE_TOP0(CLK_TOP_DBI_BCLK, "dbi_bclk", "mpll_d12", 5), +}; + +static const struct mtk_gate top_ddr3_clks[] = { + GATE_TOP0(CLK_TOP_DBI_BCLK, "dbi_bclk", "mpll_d10", 5), +}; + +static const struct mtk_gate top_clks[] = { + GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), + GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "cam_sel", 1), + GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mux_sel", 2), + GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3), + GATE_TOP0_INV(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "clk26m", 4), + GATE_TOP0_INV(CLK_TOP_SC_26M, "sc_26m", "clk26m", 6), + GATE_TOP0_INV(CLK_TOP_SC_MEM, "sc_mem", "clk26m", 7), // unk parent + GATE_TOP0(CLK_TOP_DBI_PAD0, "dbi_pad0", "dbi_bclk", 16), + GATE_TOP0(CLK_TOP_DBI_PAD1, "dbi_pad1", "dbi_bclk", 17), + GATE_TOP0(CLK_TOP_DBI_PAD2, "dbi_pad2", "dbi_bclk", 18), + GATE_TOP0(CLK_TOP_DBI_PAD3, "dbi_pad3", "dbi_bclk", 19), + GATE_TOP0_INV(CLK_TOP_MFG_PRE_491M, "mfg_pre_491m", "mpll_d3", 20), // unk parent, but i tend to think it's mainpll/3 + GATE_TOP0_INV(CLK_TOP_MFG_PRE_500M, "mfg_pre_500m", "whpll", 21), + GATE_TOP0_INV(CLK_TOP_ARMDCM, "armdcm", "clk26m", 31), // unk parent + + GATE_TOP1(CLK_TOP_EFUSE, "efuse", "clk26m", 0), + GATE_TOP1(CLK_TOP_THERMAL, "thermal", "clk26m", 1), + GATE_TOP1(CLK_TOP_APDMA, "apdma", "axi_sel", 2), + GATE_TOP1(CLK_TOP_I2C0, "i2c0", "axi_sel", 3), + GATE_TOP1(CLK_TOP_I2C1, "i2c1", "axi_sel", 4), + GATE_TOP1(CLK_TOP_NFI, "nfi", "axi_sel", 6), + GATE_TOP1(CLK_TOP_NFI_ECC, "nfi_ecc", "axi_sel", 7), + GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "axi_sel", 8), + GATE_TOP1(CLK_TOP_PWM, "pwm", "axi_sel", 9), + GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10), + GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11), + GATE_TOP1(CLK_TOP_BTIF, "btif", "axi_sel", 12), + GATE_TOP1(CLK_TOP_USB, "usb", "axi_sel", 13), + GATE_TOP1(CLK_TOP_FHCTL, "fhctl", "clk26m", 14), + GATE_TOP1(CLK_TOP_SPINFI, "spinfi", "spinfi_sel", 16), + GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17), + GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18), + GATE_TOP1(CLK_TOP_PMIC_WRAP, "pmic_wrap", "pmic_spi_sel", 20), + GATE_TOP1(CLK_TOP_SEJ, "sej", "clk26m", 21), // MT_CG_SYS_26M, AXIBUS, let it be clk26m + GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m", 22), // unk parent + GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m", 24), + GATE_TOP1(CLK_TOP_AUDIO, "audio", "audio_intbus_sel", 25), + GATE_TOP1(CLK_TOP_SPM, "spm", "clk26m", 26), + GATE_TOP1(CLK_TOP_PMIC_SPI, "pmic_spi", "clk26m", 29), + GATE_TOP1(CLK_TOP_AUXADC, "auxadc", "clk26m", 30), +}; + +static int clk_mt6572_topckgen_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + struct clk_hw *hw; + void __iomem *base; + bool is_ddr3; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + is_ddr3 = !(readl(base + CLK_CFG_0) & BIT(7)); + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_fixed_clks(topckgen_fixed_clks, + ARRAY_SIZE(topckgen_fixed_clks), clk_data); + mtk_clk_register_factors(topckgen_factors, ARRAY_SIZE(topckgen_factors), + clk_data); + mtk_clk_register_composites(dev, topckgen_muxes, + ARRAY_SIZE(topckgen_muxes), base, + &mt6572_topckgen_lock, clk_data); + mtk_clk_register_gates(dev, node, top_clks, ARRAY_SIZE(top_clks), + clk_data); + + if (is_ddr3) { + mtk_clk_register_composites(dev, topckgen_ddr3_muxes, + ARRAY_SIZE(topckgen_ddr3_muxes), + base, &mt6572_topckgen_lock, + clk_data); + mtk_clk_register_gates(dev, node, top_ddr3_clks, + ARRAY_SIZE(top_ddr3_clks), clk_data); + hw = clk_hw_register_fixed_factor(NULL, "mm_smi_src", "mainpll", + 0, 1, 5); + } else { + mtk_clk_register_composites(dev, topckgen_ddr2_muxes, + ARRAY_SIZE(topckgen_ddr2_muxes), + base, &mt6572_topckgen_lock, + clk_data); + mtk_clk_register_gates(dev, node, top_ddr2_clks, + ARRAY_SIZE(top_ddr2_clks), clk_data); + hw = clk_hw_register_fixed_factor(NULL, "mm_smi_src", "mainpll", + 0, 1, 6); + } + + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + dev_err(dev, "failed to register mm_smi_src clock: %d", ret); + goto free_data; + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) { + dev_err(dev, "failed to register clock provider: %d\n", ret); + goto free_data; + } + + return 0; + +free_data: + mtk_free_clk_data(clk_data); + return ret; +} + +static const struct mtk_clk_desc topckgen_desc = { + .fixed_clks = topckgen_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(topckgen_fixed_clks), + .factor_clks = topckgen_factors, + .num_factor_clks = ARRAY_SIZE(topckgen_factors), + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .composite_clks = topckgen_muxes, + .num_composite_clks = ARRAY_SIZE(topckgen_muxes), + .clk_lock = &mt6572_topckgen_lock, +}; + +static const struct of_device_id of_match_mt6572_topckgen[] = { + { .compatible = "mediatek,mt6572-topckgen" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_mt6572_topckgen); + +static struct platform_driver clk_mt6572_topckgen = { + .probe = clk_mt6572_topckgen_probe, + .driver = { + .name = "clk-mt6572-topckgen", + .of_match_table = of_match_mt6572_topckgen, + }, +}; +module_platform_driver(clk_mt6572_topckgen); + +MODULE_DESCRIPTION("MediaTek MT6572 topckgen clock driver"); +MODULE_LICENSE("GPL"); + diff --git a/include/dt-bindings/clock/mediatek,mt6572-clk.h b/include/dt-bindings/clock/mediatek,mt6572-clk.h index c56f5ed44d69d0..dfe9f88d01d80d 100644 --- a/include/dt-bindings/clock/mediatek,mt6572-clk.h +++ b/include/dt-bindings/clock/mediatek,mt6572-clk.h @@ -1,65 +1,129 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +// SPDX-License-Identifier: GPL-2.0+ #ifndef _DT_BINDINGS_CLK_MT6572_H #define _DT_BINDINGS_CLK_MT6572_H /* TOPCKGEN */ -#define CLK_TOP_SC_26M_SEL 0 -#define CLK_TOP_UNIV_48M_SEL 1 +#define CLK_TOP_SC_26M_SEL 0 +#define CLK_TOP_UNIV_48M_SEL 1 -#define CLK_TOP_MPLL_D2 2 -#define CLK_TOP_MPLL_D3 3 -#define CLK_TOP_MPLL_D5 4 -#define CLK_TOP_MPLL_D7 5 -#define CLK_TOP_MPLL_D4 6 -#define CLK_TOP_MPLL_D6 7 -#define CLK_TOP_MPLL_D10 8 -#define CLK_TOP_MPLL_D8 9 -#define CLK_TOP_MPLL_D12 10 -#define CLK_TOP_MPLL_D20 11 -#define CLK_TOP_MPLL_D24 12 -#define CLK_TOP_UPLL_D2 13 -#define CLK_TOP_UPLL_D3 14 -#define CLK_TOP_UPLL_D5 15 -#define CLK_TOP_UPLL_D7 16 -#define CLK_TOP_UPLL_D4 17 -#define CLK_TOP_UPLL_D6 18 -#define CLK_TOP_UPLL_D10 19 -#define CLK_TOP_UPLL_D8 20 -#define CLK_TOP_UPLL_D12 21 -#define CLK_TOP_UPLL_D20 22 -#define CLK_TOP_UPLL_D16 23 -#define CLK_TOP_UPLL_D24 24 +#define CLK_TOP_MPLL_D2 2 +#define CLK_TOP_MPLL_D3 3 +#define CLK_TOP_MPLL_D5 4 +#define CLK_TOP_MPLL_D7 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D6 7 +#define CLK_TOP_MPLL_D10 8 +#define CLK_TOP_MPLL_D8 9 +#define CLK_TOP_MPLL_D12 10 +#define CLK_TOP_MPLL_D20 11 +#define CLK_TOP_MPLL_D24 12 +#define CLK_TOP_UPLL_D2 13 +#define CLK_TOP_UPLL_D3 14 +#define CLK_TOP_UPLL_D5 15 +#define CLK_TOP_UPLL_D7 16 +#define CLK_TOP_UPLL_D4 17 +#define CLK_TOP_UPLL_D6 18 +#define CLK_TOP_UPLL_D10 19 +#define CLK_TOP_UPLL_D8 20 +#define CLK_TOP_UPLL_D12 21 +#define CLK_TOP_UPLL_D20 22 +#define CLK_TOP_UPLL_D16 23 +#define CLK_TOP_UPLL_D24 24 -#define CLK_TOP_UART0_SEL 25 -#define CLK_TOP_EMI2X_SEL 26 -#define CLK_TOP_AXI_SEL 27 -#define CLK_TOP_MFG_SEL 28 -#define CLK_TOP_MSDC0_SEL 29 -#define CLK_TOP_SPI_NAND_SEL 30 -#define CLK_TOP_CAM_SEL 31 -#define CLK_TOP_PWM_SEL 32 -#define CLK_TOP_UART1_SEL 33 -#define CLK_TOP_MSDC1_SEL 34 -#define CLK_TOP_SPM_SEL 35 -#define CLK_TOP_PMIC_SPI_SEL 36 -#define CLK_TOP_AUDIO_INTBUS_SEL 37 +#define CLK_TOP_UART0_SEL 25 +#define CLK_TOP_EMI2X_SEL 26 +#define CLK_TOP_AXI_SEL 27 +#define CLK_TOP_MFG_MUX_SEL 28 +#define CLK_TOP_MSDC0_SEL 29 +#define CLK_TOP_SPINFI_SEL 30 +#define CLK_TOP_CAM_SEL 31 +#define CLK_TOP_PWM_MM_SEL 32 +#define CLK_TOP_UART1_SEL 34 +#define CLK_TOP_MSDC1_SEL 35 +#define CLK_TOP_SPM_52M_SEL 36 +#define CLK_TOP_PMIC_SPI_SEL 37 +#define CLK_TOP_AUDIO_INTBUS_SEL 38 +#define CLK_TOP_SPINFI_PRE_SEL 39 +#define CLK_TOP_MFG_SEL 40 -#define CLK_TOP_PWM 38 -#define CLK_TOP_CAM 39 -#define CLK_TOP_MFG 40 -#define CLK_TOP_SPM 41 -#define CLK_TOP_UART0 42 -#define CLK_TOP_UART1 43 -#define CLK_TOP_MSDC0 44 -#define CLK_TOP_MSDC1 45 -#define CLK_TOP_PMIC_WRAP 46 -#define CLK_TOP_PMIC_SPI 47 -#define CLK_TOP_APXGPT 48 +/* CG0 */ +#define CLK_TOP_PWM_MM 41 +#define CLK_TOP_CAM_MM 42 +#define CLK_TOP_MFG_MM 43 +#define CLK_TOP_SPM_52M 44 +#define CLK_TOP_MIPI_26M_DBG 45 +#define CLK_TOP_DBI_BCLK 46 +#define CLK_TOP_SC_26M 47 +#define CLK_TOP_SC_MEM 48 +#define CLK_TOP_DBI_PAD0 49 +#define CLK_TOP_DBI_PAD1 50 +#define CLK_TOP_DBI_PAD2 51 +#define CLK_TOP_DBI_PAD3 52 +#define CLK_TOP_MFG_PRE_491M 53 +#define CLK_TOP_MFG_PRE_500M 54 +#define CLK_TOP_ARMDCM 55 -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIVPLL 2 -#define CLK_APMIXED_WHPLL 3 +/* CG1 */ +#define CLK_TOP_EFUSE 56 +#define CLK_TOP_THERMAL 57 +#define CLK_TOP_APDMA 58 +#define CLK_TOP_I2C0 59 +#define CLK_TOP_I2C1 60 +#define CLK_TOP_NFI 61 +#define CLK_TOP_NFI_ECC 62 +#define CLK_TOP_DEBUGSYS 63 +#define CLK_TOP_PWM 64 +#define CLK_TOP_UART0 65 +#define CLK_TOP_UART1 66 +#define CLK_TOP_BTIF 67 +#define CLK_TOP_USB 68 +#define CLK_TOP_FHCTL 69 +#define CLK_TOP_SPINFI 70 +#define CLK_TOP_MSDC0 71 +#define CLK_TOP_MSDC1 72 +#define CLK_TOP_PMIC_WRAP 73 +#define CLK_TOP_SEJ 74 +#define CLK_TOP_MEMSLP_DLYER 75 +#define CLK_TOP_APXGPT 76 +#define CLK_TOP_AUDIO 77 +#define CLK_TOP_SPM 78 +#define CLK_TOP_PMIC_SPI 79 +#define CLK_TOP_AUXADC 80 +#define CLK_TOP_NR_CLK 81 + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +//#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_WHPLL 2 + +#define CLK_INFRA_CPUSEL 0 + +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_CMDQ 2 +#define CLK_MM_SMI_CMDQ 3 +#define CLK_MM_DISP_COLOR 4 +#define CLK_MM_DISP_BLS 5 +#define CLK_MM_DISP_WDMA 6 +#define CLK_MM_DISP_RDMA 7 +#define CLK_MM_DISP_OVL 8 +#define CLK_MM_DISP_MDP_TDSHP 9 +#define CLK_MM_DISP_MDP_WROT 10 +#define CLK_MM_DISP_MDP_WDMA 11 +#define CLK_MM_DISP_MDP_RSZ1 12 +#define CLK_MM_DISP_MDP_RSZ0 13 +#define CLK_MM_DISP_MDP_RDMA 14 +#define CLK_MM_DISP_MDP_BLS_26M 15 +#define CLK_MM_CAM 16 +#define CLK_MM_SENINF 17 +#define CLK_MM_CAMTG 18 +#define CLK_MM_CODEC 19 +#define CLK_MM_DISP_FAKE_ENG 20 +#define CLK_MM_MUTEX_SLOW_CLOCK 21 +#define CLK_MM_DSI_ENGINE 22 +#define CLK_MM_DSI_DIGITAL 23 + +#define CLK_MFG_BG3D 0 #endif /* _DT_BINDINGS_CLK_MT6572_H */ From 9802a535d8090e6af89cd71446b88b318fa43383 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:22:31 +0200 Subject: [PATCH 09/69] pinctrl: mediatek: add mt6572 support Add pinctrl driver for the mt6572 SoC. Co-developed-by: Custom Firmware Signed-off-by: rva3 --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt6572.c | 310 ++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt6572.h | 1459 +++++++++++++++++ 4 files changed, 1777 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6572.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6572.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 4819617d936836..342eeb628d2f52 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -97,6 +97,13 @@ config PINCTRL_MT2701 default MACH_MT2701 select PINCTRL_MTK +config PINCTRL_MT6572 + bool "MediaTek MT6572 pin control" + depends on MACH_MT6572 + depends on OF + default MACH_MT6572 + select PINCTRL_MTK_PARIS + config PINCTRL_MT7623 bool "MediaTek MT7623 pin control with generic binding" depends on MACH_MT7623 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index ae765bd999657c..7fb67eec66d235 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o +obj-$(CONFIG_PINCTRL_MT6572) += pinctrl-mt6572.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6572.c b/drivers/pinctrl/mediatek/pinctrl-mt6572.c new file mode 100644 index 00000000000000..cd0f0fe2d2914c --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6572.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 NotMediaTek Inc. + */ + +#include "pinctrl-mtk-common-v2.h" +#include +#include "pinctrl-mtk-mt6572.h" +#include "pinctrl-paris.h" + +/* MT6572 have multiple bases to program pin configuration listed as the below: + * gpio:0x10005000, iocfg_t:0x10208000, iocfg_b:0x10209000, + * iocfg_l:0x1020A000, iocfg_r:0x1020B000, + * _i_base could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt6572_pin_mode_range[] = { + PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4), + PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4), + PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4), + PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4), + PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4), + PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4), + PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4), + PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4), + PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4), + PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4), + PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4), + PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4), + PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4), + PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4), + PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4), + PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4), + PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4), + PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4), + PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4), + PIN_FIELD_BASE(152, 153, 0, 0x0430, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6572_pin_dir_range[] = { + PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1), + PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(128, 153, 0, 0x0040, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_di_range[] = { + PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1), + PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1), + PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1), + PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1), + PIN_FIELD_BASE(128, 153, 0, 0x0240, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_do_range[] = { + PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1), + PIN_FIELD_BASE(128, 153, 0, 0x0140, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_ies_range[] = { + PINS_FIELD_BASE(0, 1, 3, 0x0000, 0x10, 0, 1), + PINS_FIELD_BASE(2, 3, 3, 0x0000, 0x10, 1, 1), + PINS_FIELD_BASE(4, 6, 3, 0x0000, 0x10, 2, 1), + PINS_FIELD_BASE(7, 7, 3, 0x0000, 0x10, 4, 1), + PINS_FIELD_BASE(8, 11, 3, 0x0000, 0x10, 3, 1), + PINS_FIELD_BASE(12, 13, 3, 0x0000, 0x10, 4, 1), + PINS_FIELD_BASE(14, 31, 3, 0x0000, 0x10, 5, 1), + PINS_FIELD_BASE(32, 39, 3, 0x0000, 0x10, 6, 1), + PINS_FIELD_BASE(40, 43, 2, 0x0000, 0x10, 2, 1), + PINS_FIELD_BASE(44, 49, 2, 0x0000, 0x10, 0, 1), + PINS_FIELD_BASE(50, 53, 2, 0x0000, 0x10, 1, 1), + PINS_FIELD_BASE(54, 54, 2, 0x0000, 0x10, 0, 1), + PINS_FIELD_BASE(55, 58, 4, 0x0000, 0x10, 0, 1), + PINS_FIELD_BASE(59, 60, 4, 0x0000, 0x10, 1, 1), + PINS_FIELD_BASE(61, 62, 4, 0x0000, 0x10, 2, 1), + PINS_FIELD_BASE(63, 66, 4, 0x0000, 0x10, 3, 1), + PINS_FIELD_BASE(87, 88, 4, 0x0000, 0x10, 4, 1), + PINS_FIELD_BASE(89, 90, 4, 0x0000, 0x10, 5, 1), + PINS_FIELD_BASE(91, 96, 4, 0x0000, 0x10, 6, 1), + PIN_FIELD_BASE(97, 102, 4, 0x0000, 0x10, 7, 1), + PINS_FIELD_BASE(103, 104, 4, 0x0000, 0x10, 13, 1), + PINS_FIELD_BASE(105, 106, 4, 0x0000, 0x10, 14, 1), + PIN_FIELD_BASE(107, 112, 1, 0x0000, 0x10, 0, 1), + PINS_FIELD_BASE(113, 114, 1, 0x0000, 0x10, 6, 1), + PINS_FIELD_BASE(115, 120, 1, 0x0010, 0x10, 0, 1), + PINS_FIELD_BASE(121, 124, 1, 0x0010, 0x10, 1, 1), + PINS_FIELD_BASE(126, 127, 1, 0x0010, 0x10, 2, 1), + PIN_FIELD_BASE(128, 129, 1, 0x0000, 0x10, 13, 1), + PINS_FIELD_BASE(130, 133, 1, 0x0000, 0x10, 7, 1), + PINS_FIELD_BASE(134, 136, 1, 0x0000, 0x10, 8, 1), + PINS_FIELD_BASE(137, 141, 1, 0x0000, 0x10, 9, 1), + PINS_FIELD_BASE(142, 145, 1, 0x0000, 0x10, 10, 1), + PINS_FIELD_BASE(146, 148, 1, 0x0000, 0x10, 11, 1), + PINS_FIELD_BASE(149, 153, 1, 0x0000, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_smt_range[] = { + PINS_FIELD_BASE(0, 1, 3, 0x0020, 0x10, 0, 1), + PINS_FIELD_BASE(2, 3, 3, 0x0020, 0x10, 1, 1), + PINS_FIELD_BASE(4, 6, 3, 0x0020, 0x10, 2, 1), + PINS_FIELD_BASE(7, 7, 3, 0x0020, 0x10, 4, 1), + PINS_FIELD_BASE(8, 11, 3, 0x0020, 0x10, 3, 1), + PINS_FIELD_BASE(12, 13, 3, 0x0020, 0x10, 4, 1), + PINS_FIELD_BASE(14, 31, 3, 0x0020, 0x10, 5, 1), + PINS_FIELD_BASE(32, 39, 3, 0x0020, 0x10, 6, 1), + PINS_FIELD_BASE(40, 43, 2, 0x0020, 0x10, 2, 1), + PINS_FIELD_BASE(44, 49, 2, 0x0020, 0x10, 0, 1), + PINS_FIELD_BASE(50, 53, 2, 0x0020, 0x10, 1, 1), + PINS_FIELD_BASE(54, 54, 2, 0x0020, 0x10, 0, 1), + PINS_FIELD_BASE(55, 58, 4, 0x0020, 0x10, 0, 1), + PINS_FIELD_BASE(59, 60, 4, 0x0020, 0x10, 1, 1), + PINS_FIELD_BASE(61, 62, 4, 0x0020, 0x10, 2, 1), + PINS_FIELD_BASE(63, 66, 4, 0x0020, 0x10, 3, 1), + PINS_FIELD_BASE(87, 88, 4, 0x0020, 0x10, 4, 1), + PINS_FIELD_BASE(89, 90, 4, 0x0020, 0x10, 5, 1), + PINS_FIELD_BASE(91, 96, 4, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(97, 102, 4, 0x0020, 0x10, 7, 1), + PINS_FIELD_BASE(103, 104, 4, 0x0020, 0x10, 13, 1), + PINS_FIELD_BASE(105, 106, 4, 0x0020, 0x10, 14, 1), + PINS_FIELD_BASE(107, 112, 1, 0x0040, 0x10, 0, 1), + PINS_FIELD_BASE(113, 114, 1, 0x0040, 0x10, 6, 1), + PINS_FIELD_BASE(115, 120, 1, 0x0050, 0x10, 0, 1), + PINS_FIELD_BASE(121, 124, 1, 0x0050, 0x10, 1, 1), + PINS_FIELD_BASE(126, 127, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(128, 129, 1, 0x0040, 0x10, 8, 1), + PINS_FIELD_BASE(130, 133, 1, 0x0040, 0x10, 2, 1), + PINS_FIELD_BASE(134, 136, 1, 0x0040, 0x10, 3, 1), + PINS_FIELD_BASE(137, 141, 1, 0x0040, 0x10, 4, 1), + PINS_FIELD_BASE(142, 145, 1, 0x0040, 0x10, 5, 1), + PINS_FIELD_BASE(146, 148, 1, 0x0040, 0x10, 6, 1), + PINS_FIELD_BASE(149, 153, 1, 0x0040, 0x10, 7, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_pu_pd_range[] = { + PIN_FIELD_BASE(0, 6, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, 3, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(8, 11, 3, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(12, 13, 3, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(14, 39, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(40, 43, 2, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, 2, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(55, 66, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(87, 106, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(107, 114, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(115, 127, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(128, 129, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(130, 153, 1, 0x0070, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_drv_range[] = { + /* + [DRV_GRP0] = { 4, 16, 4, 1 }, // index 0 + [DRV_GRP1] = { 4, 16, 4, 2 }, // index 3 (probably), TODO: figure out if this should be actually used, and not group 0 + [DRV_GRP2] = { 2, 8, 2, 1 }, // index 1 + [DRV_GRP3] = { 2, 8, 2, 2 }, // unused + [DRV_GRP4] = { 2, 16, 2, 1 }, // index 2 + */ + PINS_FIELD_BASE(0, 1, 3, 0x0080, 0x10, 0, 2), + PINS_FIELD_BASE(2, 3, 3, 0x0080, 0x10, 2, 2), + PINS_FIELD_BASE(4, 6, 3, 0x0080, 0x10, 4, 2), + PINS_FIELD_BASE(8, 11, 3, 0x0080, 0x10, 6, 2), + PINS_FIELD_BASE(7, 7, 3, 0x0080, 0x10, 8, 2), + PINS_FIELD_BASE(12, 13, 3, 0x0080, 0x10, 8, 2), + PINS_FIELD_BASE(14, 31, 3, 0x0080, 0x10, 10, 2), + PINS_FIELD_BASE(32, 39, 3, 0x0080, 0x10, 12, 2), + PINS_FIELD_BASE(40, 43, 2, 0x0060, 0x10, 8, 2), + PINS_FIELD_BASE(44, 49, 2, 0x0060, 0x10, 0, 3), + PINS_FIELD_BASE(50, 53, 2, 0x0060, 0x10, 3, 3), + PINS_FIELD_BASE(54, 54, 2, 0x0060, 0x10, 6, 2), + PINS_FIELD_BASE(55, 60, 4, 0x0060, 0x10, 0, 3), + PINS_FIELD_BASE(61, 66, 4, 0x0060, 0x10, 4, 2), + PINS_FIELD_BASE(87, 88, 4, 0x0060, 0x10, 6, 2), + PINS_FIELD_BASE(89, 90, 4, 0x0060, 0x10, 8, 2), + PINS_FIELD_BASE(91, 96, 4, 0x0060, 0x10, 10, 3), + PINS_FIELD_BASE(97, 100, 4, 0x0060, 0x10, 14, 2), + PINS_FIELD_BASE(101, 102, 4, 0x0060, 0x10, 16, 2), + PINS_FIELD_BASE(103, 104, 4, 0x0060, 0x10, 18, 2), + PINS_FIELD_BASE(107, 112, 1, 0x00D0, 0x04, 0, 2), + PINS_FIELD_BASE(115, 120, 1, 0x00D4, 0x04, 0, 2), + PINS_FIELD_BASE(121, 124, 1, 0x00D4, 0x04, 2, 2), + PINS_FIELD_BASE(126, 127, 1, 0x00D4, 0x04, 4, 2), + PINS_FIELD_BASE(128, 129, 1, 0x00D0, 0x04, 14, 2), + PINS_FIELD_BASE(130, 133, 1, 0x00D0, 0x04, 2, 2), + PINS_FIELD_BASE(134, 136, 1, 0x00D0, 0x04, 4, 2), + PINS_FIELD_BASE(137, 141, 1, 0x00D0, 0x04, 6, 2), + PINS_FIELD_BASE(142, 145, 1, 0x00D0, 0x04, 8, 2), + PINS_FIELD_BASE(146, 148, 1, 0x00D0, 0x04, 10, 2), + PINS_FIELD_BASE(149, 153, 1, 0x00D0, 0x04, 12, 2), +}; + +static const struct mtk_pin_field_calc mt6572_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 6, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(8, 11, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(12, 13, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(14, 39, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(40, 43, 2, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(44, 54, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(55, 66, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(87, 104, 4, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(107, 112, 1, 0x00A0, 0x10, 0, 1), + PIN_FIELD_BASE(115, 127, 1, 0x00C0, 0x10, 0, 1), + PIN_FIELD_BASE(128, 129, 1, 0x00B0, 0x10, 0, 1), + PIN_FIELD_BASE(130, 148, 1, 0x00A0, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_r0_range[] = { + PIN_FIELD_BASE(44, 44, 2, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(45, 45, 2, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(46, 46, 2, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 2, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(52, 52, 2, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(53, 53, 2, 0x0040, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt6572_pin_r1_range[] = { + PIN_FIELD_BASE(44, 44, 2, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(45, 45, 2, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 2, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 2, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 2, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 2, 0x0040, 0x10, 19, 1), +}; + +static const struct mtk_pin_reg_calc mt6572_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6572_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6572_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6572_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6572_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6572_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6572_pin_ies_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6572_pin_pu_pd_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6572_pin_pupd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6572_pin_drv_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6572_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6572_pin_r1_range), +}; + +static const char * const mt6572_pinctrl_register_base_names[] = { + "gpio", "iocfg_t", "iocfg_b", "iocfg_l", "iocfg_r", +}; + +static const struct mtk_eint_hw mt6572_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = 26, + .db_cnt = 26, + .db_time = debounce_time_mt2701, +}; + +static const struct mtk_pin_soc mt6572_data = { + .reg_cal = mt6572_reg_cals, + .pins = mtk_pins_mt6572, + .npins = ARRAY_SIZE(mtk_pins_mt6572), + .ngrps = ARRAY_SIZE(mtk_pins_mt6572), + .eint_hw = &mt6572_eint_hw, + .gpio_m = 0, + .ies_present = true, + .base_names = mt6572_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6572_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt6572_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6572-pinctrl", .data = &mt6572_data }, + { } +}; +MODULE_DEVICE_TABLE(of, mt6572_pinctrl_of_match); + +static struct platform_driver mt6572_pinctrl_driver = { + .driver = { + .name = "mt6572-pinctrl", + .of_match_table = mt6572_pinctrl_of_match, + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6572_pinctrl_init(void) +{ + return platform_driver_register(&mt6572_pinctrl_driver); +} +arch_initcall(mt6572_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6572 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6572.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6572.h new file mode 100644 index 00000000000000..350f2ba81e9533 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6572.h @@ -0,0 +1,1459 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 Me, myself and I + */ + +#ifndef __PINCTRL_MTK_MT6572_H +#define __PINCTRL_MTK_MT6572_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt6572[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "SIM2_SCLK"), + MTK_FUNCTION(2, "SIM1_SCLK"), + MTK_FUNCTION(7, "CONN_MCU_TMS") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SIM2_SIO"), + MTK_FUNCTION(2, "SIM1_SIO"), + MTK_FUNCTION(7, "CONN_MCU_TRST_B") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SIM1_SCLK"), + MTK_FUNCTION(2, "SIM2_SCLK"), + MTK_FUNCTION(7, "CONN_MCU_TDI") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SIM1_SIO"), + MTK_FUNCTION(2, "SIM2_SIO"), + MTK_FUNCTION(7, "CONN_MCU_TCK") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "AUD_CLK"), + MTK_FUNCTION(3, "AUD_ADC_CK"), + MTK_FUNCTION(7, "CONN_MCU_DBGI_N") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "AUD_MISO"), + MTK_FUNCTION(3, "AUD_ADC_DAT_IN"), + MTK_FUNCTION(7, "CONN_MCU_DBGACK_N") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "AUD_MOSI"), + MTK_FUNCTION(3, "AUD_ADC_WS"), + MTK_FUNCTION(7, "CONN_MCU_TDO") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(1, 16), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "PMIC_EINT") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "PMIC_SPI_CSN") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "PMIC_SPI_SCK") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "PMIC_SPI_MOSI") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "PMIC_SPI_MISO") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SRCLKENA") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "LPD0"), + MTK_FUNCTION(2, "PWM3"), + MTK_FUNCTION(4, "DPI_B0"), + MTK_FUNCTION(5, "DBG_OUT8"), + MTK_FUNCTION(6, "DBG_OUT0"), + MTK_FUNCTION(7, "CONN_MCU_TMS") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "LPD1"), + MTK_FUNCTION(2, "PWM4"), + MTK_FUNCTION(4, "DPI_B1"), + MTK_FUNCTION(5, "DBG_OUT9"), + MTK_FUNCTION(6, "DBG_OUT1"), + MTK_FUNCTION(7, "CONN_MCU_TRST_B") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "LPD2"), + MTK_FUNCTION(2, "PWM5"), + MTK_FUNCTION(4, "DPI_B2"), + MTK_FUNCTION(5, "DBG_OUT10"), + MTK_FUNCTION(6, "DBG_OUT2"), + MTK_FUNCTION(7, "CONN_MCU_TDI") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "LPD3"), + MTK_FUNCTION(4, "DPI_B3"), + MTK_FUNCTION(5, "DBG_OUT11"), + MTK_FUNCTION(6, "DBG_OUT3"), + MTK_FUNCTION(7, "CONN_MCU_TCK") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "LPD4"), + MTK_FUNCTION(4, "DPI_B4"), + MTK_FUNCTION(5, "DBG_OUT12"), + MTK_FUNCTION(6, "DBG_OUT4"), + MTK_FUNCTION(7, "CONN_MCU_DBGI_N") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "LPD5"), + MTK_FUNCTION(4, "DPI_B5"), + MTK_FUNCTION(5, "DBG_OUT13"), + MTK_FUNCTION(6, "DBG_OUT5"), + MTK_FUNCTION(7, "CONN_MCU_DBGACK_N") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "LPD6"), + MTK_FUNCTION(4, "DPI_G0"), + MTK_FUNCTION(5, "DBG_OUT14"), + MTK_FUNCTION(6, "DBG_OUT6"), + MTK_FUNCTION(7, "CONN_MCU_TDO") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "LPD7"), + MTK_FUNCTION(3, "KCOL7"), + MTK_FUNCTION(4, "DPI_G1"), + MTK_FUNCTION(5, "DBG_OUT15"), + MTK_FUNCTION(6, "DBG_OUT7") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "LPD8"), + MTK_FUNCTION(2, "PWM_BL"), + MTK_FUNCTION(4, "DPI_G2"), + MTK_FUNCTION(6, "DBG_OUT8"), + MTK_FUNCTION(7, "CONN_GPIO0") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "LPD9"), + MTK_FUNCTION(2, "SRCLKENAI"), + MTK_FUNCTION(4, "DPI_G3"), + MTK_FUNCTION(6, "DBG_OUT9"), + MTK_FUNCTION(7, "CONN_GPIO1") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "LPD10"), + MTK_FUNCTION(2, "MC1_INS"), + MTK_FUNCTION(4, "DPI_G4"), + MTK_FUNCTION(6, "DBG_OUT10"), + MTK_FUNCTION(7, "CONN_GPIO2") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "LPD11"), + MTK_FUNCTION(2, "EINT5"), + MTK_FUNCTION(4, "DPI_G5"), + MTK_FUNCTION(6, "DBG_OUT11"), + MTK_FUNCTION(7, "CONN_GPIO3") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "LPD12"), + MTK_FUNCTION(2, "EINT4"), + MTK_FUNCTION(4, "DPI_R0"), + MTK_FUNCTION(5, "MD_EINT3"), + MTK_FUNCTION(6, "DBG_OUT12"), + MTK_FUNCTION(7, "CONN_GPIO4") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "LPD13"), + MTK_FUNCTION(2, "EINT3"), + MTK_FUNCTION(4, "DPI_R1"), + MTK_FUNCTION(5, "MD_EINT2"), + MTK_FUNCTION(6, "DBG_OUT13"), + MTK_FUNCTION(7, "CONN_GPIO5") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "LPD14"), + MTK_FUNCTION(2, "EINT2"), + MTK_FUNCTION(4, "DPI_R2"), + MTK_FUNCTION(5, "MD_EINT1"), + MTK_FUNCTION(6, "DBG_OUT14"), + MTK_FUNCTION(7, "CONN_GPIO6") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "LPD15"), + MTK_FUNCTION(2, "EINT1"), + MTK_FUNCTION(4, "DPI_R3"), + MTK_FUNCTION(5, "MD_EINT0"), + MTK_FUNCTION(6, "DBG_OUT15"), + MTK_FUNCTION(7, "CONN_GPIO7") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "LPD16"), + MTK_FUNCTION(2, "EINT0"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "DPI_R4"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "LPD17"), + MTK_FUNCTION(2, "EINT6"), + MTK_FUNCTION(3, "KROW7"), + MTK_FUNCTION(4, "DPI_R5"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(4, "NFI0"), + MTK_FUNCTION(7, "CONN_MCU_TMS") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(4, "NFI1"), + MTK_FUNCTION(7, "CONN_MCU_TRST_B") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(4, "NFI2"), + MTK_FUNCTION(7, "CONN_MCU_TDI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(4, "NFI3"), + MTK_FUNCTION(7, "CONN_MCU_TCK") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(4, "NFI4"), + MTK_FUNCTION(7, "CONN_MCU_DBGI_N") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(4, "NFI5"), + MTK_FUNCTION(7, "CONN_MCU_DBGACK_N") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(4, "NFI6"), + MTK_FUNCTION(7, "CONN_MCU_TDO") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(4, "NFI7") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(4, "NFI8") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(4, "NFI9") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(4, "NFI10") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(4, "NFI11") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MC0_CK"), + MTK_FUNCTION(3, "LPTE"), + MTK_FUNCTION(4, "NFI12") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MC0_CMD"), + MTK_FUNCTION(3, "LPA0"), + MTK_FUNCTION(4, "NFI13") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MC0_DAT0"), + MTK_FUNCTION(3, "LPWRB"), + MTK_FUNCTION(4, "NFI14") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MC0_DAT1"), + MTK_FUNCTION(3, "LPRDB"), + MTK_FUNCTION(4, "NFI15") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "MC0_DAT2"), + MTK_FUNCTION(4, "NFI16") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "MC0_DAT3"), + MTK_FUNCTION(3, "LPCE0B"), + MTK_FUNCTION(4, "NFI17") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "MC0_DAT4"), + MTK_FUNCTION(2, "PWM_BL"), + MTK_FUNCTION(4, "NFI18") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "MC0_DAT5"), + MTK_FUNCTION(2, "EINT13"), + MTK_FUNCTION(4, "NFI19") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "MC0_DAT6"), + MTK_FUNCTION(2, "EINT14"), + MTK_FUNCTION(4, "NFI20") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "MC0_DAT7"), + MTK_FUNCTION(2, "MC1_INS"), + MTK_FUNCTION(4, "NFI21") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "MC0_RSTB"), + MTK_FUNCTION(2, "EINT12"), + MTK_FUNCTION(3, "LRSTB"), + MTK_FUNCTION(4, "NFI22") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SD_DAT0"), + MTK_FUNCTION(2, "LPTE"), + MTK_FUNCTION(3, "SFCK"), + MTK_FUNCTION(5, "DPI_CK") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SD_DAT1"), + MTK_FUNCTION(2, "LPA0"), + MTK_FUNCTION(3, "SFCS1"), + MTK_FUNCTION(4, "EINT10"), + MTK_FUNCTION(5, "DPI_DE") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SD_DAT2"), + MTK_FUNCTION(2, "LPWRB"), + MTK_FUNCTION(3, "SFIN"), + MTK_FUNCTION(4, "EINT11"), + MTK_FUNCTION(5, "DPI_VSYNC") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SD_DAT3"), + MTK_FUNCTION(2, "LPRDB"), + MTK_FUNCTION(3, "SFHOLD"), + MTK_FUNCTION(4, "EINT12"), + MTK_FUNCTION(5, "DPI_HSYNC") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SD_CK"), + MTK_FUNCTION(2, "LRSTB"), + MTK_FUNCTION(3, "SFOUT") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SD_CMD"), + MTK_FUNCTION(2, "LPCE0B"), + MTK_FUNCTION(3, "SFWP_B"), + MTK_FUNCTION(4, "EINT9"), + MTK_FUNCTION(5, "LSCE0B") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(6, "DBG_OUT0") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(6, "DBG_OUT1") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(3, "EINT3"), + MTK_FUNCTION(5, "TDD_TXD"), + MTK_FUNCTION(6, "DBG_OUT2"), + MTK_FUNCTION(7, "CONN_GPIO16") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(3, "EINT13"), + MTK_FUNCTION(5, "MD_DSPJTD"), + MTK_FUNCTION(6, "DBG_OUT3"), + MTK_FUNCTION(7, "CONN_GPIO17") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "CMDAT2"), + MTK_FUNCTION(3, "EINT7"), + MTK_FUNCTION(5, "MD_DSPJTCK"), + MTK_FUNCTION(6, "DBG_OUT4"), + MTK_FUNCTION(7, "CONN_GPIO18") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "CMDAT3"), + MTK_FUNCTION(3, "EINT8"), + MTK_FUNCTION(5, "MD_DSPJTMS"), + MTK_FUNCTION(6, "DBG_OUT5"), + MTK_FUNCTION(7, "CONN_GPIO19") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "MIPI_RDP0_A"), + MTK_FUNCTION(2, "CMDAT4"), + MTK_FUNCTION(3, "MC1_INS") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "MIPI_RDN0_A"), + MTK_FUNCTION(2, "CMDAT5"), + MTK_FUNCTION(3, "KCOL3") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "MIPI_RDP1_A"), + MTK_FUNCTION(2, "CMDAT6"), + MTK_FUNCTION(3, "KCOL4"), + MTK_FUNCTION(4, "EINT7") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "MIPI_RDN1_A"), + MTK_FUNCTION(2, "CMDAT7"), + MTK_FUNCTION(3, "KCOL5"), + MTK_FUNCTION(4, "EINT8") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "MIPI_RCP_A"), + MTK_FUNCTION(2, "CMHSYNC"), + MTK_FUNCTION(3, "KCOL6") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "MIPI_RCN_A"), + MTK_FUNCTION(2, "CMVSYNC"), + MTK_FUNCTION(3, "KCOL7") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "MIPI_RDP0"), + MTK_FUNCTION(3, "EINT3"), + MTK_FUNCTION(4, "MC1_INS") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "MIPI_RDN0"), + MTK_FUNCTION(3, "EINT4"), + MTK_FUNCTION(4, "KCOL3") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "MIPI_RDP1"), + MTK_FUNCTION(3, "EINT7"), + MTK_FUNCTION(4, "KCOL4") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "MIPI_RDN1"), + MTK_FUNCTION(3, "EINT8"), + MTK_FUNCTION(4, "KCOL5") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "MIPI_RCP"), + MTK_FUNCTION(2, "EINT6"), + MTK_FUNCTION(3, "MC1_INS"), + MTK_FUNCTION(4, "KCOL6") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "MIPI_RCN"), + MTK_FUNCTION(3, "SRCLKENAI"), + MTK_FUNCTION(4, "KCOL7") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "MIPI_TDP0"), + MTK_FUNCTION(3, "EINT9") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "MIPI_TDN0"), + MTK_FUNCTION(3, "EINT10") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "MIPI_TDP1"), + MTK_FUNCTION(3, "EINT11") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MIPI_TDN1"), + MTK_FUNCTION(3, "EINT12") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MIPI_TCP"), + MTK_FUNCTION(3, "EINT13") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MIPI_TCN"), + MTK_FUNCTION(3, "EINT14"), + MTK_FUNCTION(4, "SRCLKENAI") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MIPI_TDP2"), + MTK_FUNCTION(3, "MD_EINT0") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MIPI_TDN2"), + MTK_FUNCTION(3, "MD_EINT1"), + MTK_FUNCTION(4, "MC1_INS") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "EINT8"), + MTK_FUNCTION(2, "SFCS2"), + MTK_FUNCTION(3, "KCOL3"), + MTK_FUNCTION(4, "TDD_TXD"), + MTK_FUNCTION(5, "JTCK"), + MTK_FUNCTION(6, "DBG_OUT6"), + MTK_FUNCTION(7, "CONN_GPIO20") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "EINT9"), + MTK_FUNCTION(2, "MC1_INS"), + MTK_FUNCTION(3, "KCOL4"), + MTK_FUNCTION(5, "JTMS"), + MTK_FUNCTION(6, "DBG_OUT7"), + MTK_FUNCTION(7, "CONN_GPIO21") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "EINT14"), + MTK_FUNCTION(2, "SCL_1_1"), + MTK_FUNCTION(3, "KROW7"), + MTK_FUNCTION(4, "SIM1_SRST"), + MTK_FUNCTION(5, "JTDI"), + MTK_FUNCTION(6, "DBG_OUT8"), + MTK_FUNCTION(7, "CONN_GPIO22") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "EINT15"), + MTK_FUNCTION(2, "SDA_1_1"), + MTK_FUNCTION(3, "KCOL7"), + MTK_FUNCTION(4, "SIM2_SRST"), + MTK_FUNCTION(5, "JTDO"), + MTK_FUNCTION(6, "DBG_OUT9"), + MTK_FUNCTION(7, "CONN_GPIO23") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "MC1_CK"), + MTK_FUNCTION(4, "JTMS"), + MTK_FUNCTION(5, "TDD_TMS"), + MTK_FUNCTION(7, "CONN_DSP_JDI") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "MC1_CMD"), + MTK_FUNCTION(5, "TDD_TRSTN"), + MTK_FUNCTION(7, "CONN_DSP_JDO") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "MC1_DAT0"), + MTK_FUNCTION(4, "JTCK"), + MTK_FUNCTION(5, "TDD_TCK"), + MTK_FUNCTION(7, "CONN_DSP_JCK") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "MC1_DAT1"), + MTK_FUNCTION(5, "DAI_RX_GPIO"), + MTK_FUNCTION(6, "TDD_TXD") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "MC1_DAT2"), + MTK_FUNCTION(4, "JTDI"), + MTK_FUNCTION(5, "TDD_TDI"), + MTK_FUNCTION(7, "CONN_DSP_JINTP") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "MC1_DAT3"), + MTK_FUNCTION(4, "JTDO"), + MTK_FUNCTION(5, "TDD_TDO"), + MTK_FUNCTION(7, "CONN_DSP_JMS") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "SPI_CS"), + MTK_FUNCTION(2, "I2S_IN_WS"), + MTK_FUNCTION(3, "KROW3"), + MTK_FUNCTION(4, "EINT3"), + MTK_FUNCTION(5, "DPI_B6"), + MTK_FUNCTION(6, "DBG_OUT0"), + MTK_FUNCTION(7, "MD_CDMA_GPS_SYNC") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "SPI_SCK"), + MTK_FUNCTION(2, "I2S_IN_CK"), + MTK_FUNCTION(3, "KROW4"), + MTK_FUNCTION(4, "EINT4"), + MTK_FUNCTION(5, "DPI_B7"), + MTK_FUNCTION(6, "DBG_OUT1"), + MTK_FUNCTION(7, "MD_EXT_FRAME_SYNC") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "SPI_MOSI"), + MTK_FUNCTION(2, "I2S_IN_DAT"), + MTK_FUNCTION(3, "KROW5"), + MTK_FUNCTION(4, "EINT7"), + MTK_FUNCTION(5, "DPI_G6"), + MTK_FUNCTION(6, "DBG_OUT2") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "SPI_MISO"), + MTK_FUNCTION(2, "SRCLKENAI"), + MTK_FUNCTION(3, "KROW6"), + MTK_FUNCTION(4, "EINT14"), + MTK_FUNCTION(5, "DPI_G7"), + MTK_FUNCTION(6, "DBG_OUT3") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "EINT15"), + MTK_FUNCTION(3, "SCL_1_2"), + MTK_FUNCTION(4, "JTCK"), + MTK_FUNCTION(5, "DPI_R6") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "PWM_BL"), + MTK_FUNCTION(3, "SDA_1_2"), + MTK_FUNCTION(4, "JTMS"), + MTK_FUNCTION(5, "DPI_R7") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(5, "MD_URXD"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(5, "MD_UTXD"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SCL_0_0") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SDA_0_0") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "KCOL0"), + MTK_FUNCTION(6, "DBG_OUT10"), + MTK_FUNCTION(7, "CONN_GPIO24") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "KCOL1"), + MTK_FUNCTION(2, "EINT6"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(5, "MD_URXD"), + MTK_FUNCTION(6, "DBG_OUT11"), + MTK_FUNCTION(7, "CONN_GPIO25") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "KCOL2"), + MTK_FUNCTION(4, "JTCK"), + MTK_FUNCTION(6, "DBG_OUT12"), + MTK_FUNCTION(7, "CONN_GPIO26") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "KROW0"), + MTK_FUNCTION(6, "DBG_OUT13"), + MTK_FUNCTION(7, "CONN_GPIO27") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "KROW1"), + MTK_FUNCTION(2, "LPTE_2ND"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(5, "MD_UTXD"), + MTK_FUNCTION(6, "DBG_OUT14"), + MTK_FUNCTION(7, "CONN_GPIO28") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "KROW2"), + MTK_FUNCTION(4, "JTMS"), + MTK_FUNCTION(6, "DBG_OUT15"), + MTK_FUNCTION(7, "CONN_GPIO29") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "SCL_1_0") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_FIXED, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "SDA_1_0") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "CONN_WB_CTRL5") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "CONN_WB_CTRL4") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "CONN_WB_CTRL3") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "CONN_WB_CTRL2") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "CONN_WB_CTRL1") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "CONN_WB_CTRL0") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "CONN_SEN") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "CONN_SDATA") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "CONN_SCLK") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "CONN_RSTB") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO125") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "CONN_F2W_CK") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "CONN_F2W_DAT") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT2"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "SRCLKENAI"), + MTK_FUNCTION(5, "MD_CLKM0"), + MTK_FUNCTION(6, "LSCK"), + MTK_FUNCTION(7, "CONN_GPIO30") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(2, 1), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT1"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "USB_IDDIG"), + MTK_FUNCTION(5, "MD_CLKM1"), + MTK_FUNCTION(6, "LSDA"), + MTK_FUNCTION(7, "CONN_GPIO31") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(6, "DBG_OUT0"), + MTK_FUNCTION(7, "CONN_GPIO0") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(6, "DBG_OUT1"), + MTK_FUNCTION(7, "CONN_GPIO1") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(6, "DBG_OUT2"), + MTK_FUNCTION(7, "CONN_GPIO2") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(6, "DBG_OUT3"), + MTK_FUNCTION(7, "CONN_GPIO3") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "I2S_OUT_WS"), + MTK_FUNCTION(6, "DBG_OUT4"), + MTK_FUNCTION(7, "CONN_GPIO4") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(4, "EINT0"), + MTK_FUNCTION(5, "I2S_OUT_CK"), + MTK_FUNCTION(6, "DBG_OUT5"), + MTK_FUNCTION(7, "CONN_GPIO5") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "ANT_SEL2"), + MTK_FUNCTION(3, "SFCS2_MX"), + MTK_FUNCTION(4, "EINT2"), + MTK_FUNCTION(5, "I2S_OUT_DAT"), + MTK_FUNCTION(6, "DBG_OUT6"), + MTK_FUNCTION(7, "CONN_GPIO6") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "BSI2_DATA"), + MTK_FUNCTION(3, "SCL_1_3"), + MTK_FUNCTION(6, "DBG_OUT7"), + MTK_FUNCTION(7, "CONN_GPIO7") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "BSI2_CLK"), + MTK_FUNCTION(3, "SDA_1_3"), + MTK_FUNCTION(6, "DBG_OUT8"), + MTK_FUNCTION(7, "CONN_GPIO8") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(6, "DBG_OUT9"), + MTK_FUNCTION(7, "CONN_GPIO9") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(4, "EINT6"), + MTK_FUNCTION(6, "DBG_OUT10"), + MTK_FUNCTION(7, "CONN_GPIO10") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(6, "DBG_OUT11"), + MTK_FUNCTION(7, "CONN_GPIO11") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(2, "LSA0"), + MTK_FUNCTION(3, "EINT7"), + MTK_FUNCTION(4, "I2S_IN_WS"), + MTK_FUNCTION(5, "KROW3"), + MTK_FUNCTION(6, "DBG_OUT12"), + MTK_FUNCTION(7, "CONN_GPIO12") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "EINT4"), + MTK_FUNCTION(4, "I2S_IN_CK"), + MTK_FUNCTION(5, "KROW4"), + MTK_FUNCTION(6, "DBG_OUT13"), + MTK_FUNCTION(7, "CONN_GPIO13") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "EINT5"), + MTK_FUNCTION(4, "I2S_IN_DAT"), + MTK_FUNCTION(5, "KROW5"), + MTK_FUNCTION(6, "DBG_OUT14"), + MTK_FUNCTION(7, "CONN_GPIO14") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(2, "PWM_BL"), + MTK_FUNCTION(3, "EINT8"), + MTK_FUNCTION(4, "LSDI"), + MTK_FUNCTION(5, "KROW6"), + MTK_FUNCTION(6, "DBG_OUT15"), + MTK_FUNCTION(7, "CONN_GPIO15") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "TXBPI") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "VM0") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "VM1") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "BSI_EN") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "BSI_CLK") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "BSI_DATA0") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "BSI_DATA1") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "BSI_DATA2") + ) +}; + +#endif /* __PINCTRL_MTK_MT6572_H */ From 0e920fc54e51ec0f7247dd048581da08f8927d58 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:35:00 +0200 Subject: [PATCH 10/69] pmdomain: mediatek: mtk-pm-domain: add mt6572 support XXX: fixup other pds Signed-off-by: rva3 --- drivers/pmdomain/mediatek/mt6572-pm-domains.h | 42 +++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 +++ include/linux/soc/mediatek/infracfg.h | 5 +++ 3 files changed, 52 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt6572-pm-domains.h diff --git a/drivers/pmdomain/mediatek/mt6572-pm-domains.h b/drivers/pmdomain/mediatek/mt6572-pm-domains.h new file mode 100644 index 00000000000000..342ed16105693e --- /dev/null +++ b/drivers/pmdomain/mediatek/mt6572-pm-domains.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SOC_MEDIATEK_MT6572_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT6572_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT6572 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt6572[] = { + [MT6572_POWER_DOMAIN_DIS] = { + .name = "dis", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT6572_TOP_AXI_PROT_EN_DIS), + }, + }, + [MT6572_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + }, +}; + +static const struct scpsys_soc_data mt6572_scpsys_data = { + .domains_data = scpsys_domain_data_mt6572, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6572), +}; + +#endif /* __SOC_MEDIATEK_MT6572_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index e2800aa1bc597f..47f9205f3b2af2 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -18,6 +18,7 @@ #include #include +#include "mt6572-pm-domains.h" #include "mt6735-pm-domains.h" #include "mt6795-pm-domains.h" #include "mt6893-pm-domains.h" @@ -1118,6 +1119,10 @@ static int scpsys_get_bus_protection(struct device *dev, struct scpsys *scpsys) } static const struct of_device_id scpsys_of_match[] = { + { + .compatible = "mediatek,mt6572-power-controller", + .data = &mt6572_scpsys_data, + }, { .compatible = "mediatek,mt6735-power-controller", .data = &mt6735_scpsys_data, diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 9956e18c5ffa93..cca83c212454ae 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -439,6 +439,11 @@ BIT(26) | BIT(27) | \ BIT(28)) +/* XXX: no idea about these names, using MT2701 naming convention... */ +#define MT6572_TOP_AXI_PROT_EN_CONN_M BIT(0) +#define MT6572_TOP_AXI_PROT_EN_CONN_S BIT(4) +#define MT6572_TOP_AXI_PROT_EN_DIS BIT(11) + #define INFRA_TOPAXI_PROTECTEN 0x0220 #define INFRA_TOPAXI_PROTECTSTA1 0x0228 #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 From ca531e066890b548f7297c63fb0ab2d913674b92 Mon Sep 17 00:00:00 2001 From: rva3 Date: Tue, 3 Mar 2026 17:31:00 +0200 Subject: [PATCH 11/69] memory: mtk-smi: add support for mt65xx smi common The mt65xx SoC family uses an earlier version of the SMI, which we refer to as gen 0. Unlike gen 1 or gen 2, gen 0 requires simultaneous access to two distinct MMIO ranges: an AO base for IOMMU configuration and ext base for OSTD, FIFO, and bandwidth limiter setup. Remove the union in struct mtk_smi to allow simultaneous use of smi_ao_base and base. Refactor the probe function into a switch statement to handle the different generation requirements cleanly. Signed-off-by: rva3 --- drivers/memory/mtk-smi.c | 74 +++++++++++++++++++++++----------------- 1 file changed, 43 insertions(+), 31 deletions(-) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index aaeba8ab211e97..b931219bc0c5e1 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -100,6 +100,7 @@ struct mtk_smi_reg_pair { }; enum mtk_smi_type { + MTK_SMI_GEN0, MTK_SMI_GEN1, MTK_SMI_GEN2, /* gen2 smi common */ MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ @@ -141,10 +142,8 @@ struct mtk_smi { unsigned int clk_num; struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; struct clk *clk_async; /*only needed by mt2701*/ - union { - void __iomem *smi_ao_base; /* only for gen1 */ - void __iomem *base; /* only for gen2 */ - }; + void __iomem *smi_ao_base; + void __iomem *base; struct device *smi_common_dev; /* for sub common */ const struct mtk_smi_common_plat *plat; }; @@ -883,31 +882,42 @@ static int mtk_smi_common_probe(struct platform_device *pdev) if (ret) return ret; - /* - * for mtk smi gen 1, we need to get the ao(always on) base to config - * m4u port, and we need to enable the aync clock for transform the smi - * clock into emi clock domain, but for mtk smi gen2, there's no smi ao - * base. - */ - if (common->plat->type == MTK_SMI_GEN1) { - common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(common->smi_ao_base)) - return PTR_ERR(common->smi_ao_base); - - common->clk_async = devm_clk_get_enabled(dev, "async"); - if (IS_ERR(common->clk_async)) - return PTR_ERR(common->clk_async); - } else { - common->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(common->base)) - return PTR_ERR(common->base); - } - - /* link its smi-common if this is smi-sub-common */ - if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { - ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); - if (ret < 0) - return ret; + switch (common->plat->type) { + case MTK_SMI_GEN0: + /* + * gen 0 uses 2 mmio ranges: ao base for iommu configuration, + * and ext base for ostd, fifo and bw limiter setup + */ + common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(common->smi_ao_base)) + return PTR_ERR(common->smi_ao_base); + common->base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(common->base)) + return PTR_ERR(common->base); + break; + case MTK_SMI_GEN1: + /* + * gen 1 needs async clock to transform the smi clock to the + * emi clock domain + */ + common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(common->smi_ao_base)) + return PTR_ERR(common->smi_ao_base); + common->clk_async = devm_clk_get_enabled(dev, "async"); + if (IS_ERR(common->clk_async)) + return PTR_ERR(common->clk_async); + break; + case MTK_SMI_GEN2: + common->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(common->base)) + return PTR_ERR(common->base); + break; + case MTK_SMI_GEN2_SUB_COMM: + /* link its smi-common if this is smi-sub-common */ + ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); + if (ret < 0) + return ret; + break; } pm_runtime_enable(dev); @@ -936,13 +946,15 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) if (ret) return ret; - if (common->plat->type != MTK_SMI_GEN2) + if (common->plat->type != MTK_SMI_GEN0 && common->plat->type != MTK_SMI_GEN2) return 0; for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) writel_relaxed(init[i].value, common->base + init[i].offset); - writel(bus_sel, common->base + SMI_BUS_SEL); + if (common->plat->type == MTK_SMI_GEN2) + writel(bus_sel, common->base + SMI_BUS_SEL); + return 0; } From 8f9d18c0c8c0ff0ce0c187276fc2f7b6c2d42b1f Mon Sep 17 00:00:00 2001 From: rva3 Date: Tue, 3 Mar 2026 23:04:41 +0200 Subject: [PATCH 12/69] memory: mtk-smi: add mt6572 support Add platform data for the SMI common on the mt6572 SoC. Signed-off-by: rva3 --- drivers/memory/mtk-smi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index b931219bc0c5e1..cd209aad6cbbad 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -22,6 +22,10 @@ /* SMI COMMON */ #define SMI_L1LEN 0x100 +#define MT6572_SMI_L1LEN 0x200 + +#define MT6572_SMI_L1_ARB0 0x204 +#define MT6572_SMI_L1_ARB1 0x208 #define SMI_L1_ARB 0x200 #define SMI_BUS_SEL 0x220 @@ -738,6 +742,14 @@ static struct platform_driver mtk_smi_larb_driver = { } }; +static const struct mtk_smi_reg_pair mtk_smi_common_mt6572_init[SMI_COMMON_INIT_REGS_NR] = { + {MT6572_SMI_L1LEN, 0x3}, + {MT6572_SMI_L1_ARB0, 0}, + {MT6572_SMI_L1_ARB1, 0}, + {SMI_M4U_TH, 0x29ca7}, + {SMI_READ_FIFO_TH, 0x320}, +}; + static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { {SMI_L1_ARB, 0x1b}, {SMI_M4U_TH, 0xce810c85}, @@ -754,6 +766,11 @@ static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_ {SMI_DUMMY, 0x1}, }; +static const struct mtk_smi_common_plat mtk_smi_common_mt6572 = { + .type = MTK_SMI_GEN0, + .init = mtk_smi_common_mt6572_init, +}; + static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { .type = MTK_SMI_GEN1, }; @@ -842,6 +859,7 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = { static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, + {.compatible = "mediatek,mt6572-smi-common", .data = &mtk_smi_common_mt6572}, {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795}, {.compatible = "mediatek,mt6893-smi-common", .data = &mtk_smi_common_mt6893}, From 23e1e05801d5a510276c9d9b1616ab27f132c26d Mon Sep 17 00:00:00 2001 From: rva3 Date: Wed, 4 Mar 2026 03:55:31 +0200 Subject: [PATCH 13/69] memory: mtk-smi: add support for mt65xx smi larb The mt65xx SoC family utilizes a larb design that incorporates features from both gen 1 and gen 2 architectures. Introduce a specific configuration callback for this generation, which implements the port security configuration typical for gen 1 while including the ostd settings found in gen 2. Additionally, add a bandwidth calibration flag for some of the gen 0 SoCs. Signed-off-by: rva3 --- drivers/memory/mtk-smi.c | 66 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index cd209aad6cbbad..d3762a0e499bc1 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -41,6 +41,7 @@ #define SMI_DUMMY 0x444 /* SMI LARB */ +#define SMI_LARB_STAT 0x0 #define SMI_LARB_SLP_CON 0xc #define SLP_PROT_EN BIT(0) #define SLP_PROT_RDY BIT(16) @@ -52,9 +53,14 @@ #define SMI_LARB_SW_FLAG 0x40 #define SMI_LARB_SW_FLAG_1 0x1 +#define SMI_LARB_BWFILTER_EN 0x60 +#define SMI_LARB_OSTD_CTRL_EN 0x64 + #define SMI_LARB_OSTDL_PORT 0x200 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) +#define SMI_LARB_FIFO_STAT0 0x600 + /* Below are about mmu enable registers, they are different in SoCs */ /* gen1: mt2701 */ #define REG_SMI_SECUR_CON_BASE 0x5c0 @@ -96,6 +102,7 @@ #define MTK_SMI_FLAG_SW_FLAG BIT(1) #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) #define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3) +#define MTK_SMI_FLAG_BW_CALIBRATE BIT(4) #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) struct mtk_smi_reg_pair { @@ -191,6 +198,65 @@ static const struct component_ops mtk_smi_larb_component_ops = { .unbind = mtk_smi_larb_unbind, }; +static int mtk_smi_larb_config_port_gen0(struct device *dev) +{ + struct mtk_smi_larb *larb = dev_get_drvdata(dev); + const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; + struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); + const u8 *larbostd = larb_gen->ostd ? larb_gen->ostd[larb->larbid] : + NULL; + int i, m4u_port_id, larb_port_num; + u32 sec_con_val, reg_val, tmp; + int ret; + + m4u_port_id = larb_gen->port_in_larb[larb->larbid]; + larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] - m4u_port_id; + + /* gen 1 part */ + for (i = 0; i < larb_port_num; i++, m4u_port_id++) { + if (*larb->mmu & BIT(i)) { + sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); + } else { + continue; + } + + reg_val = readl(common->smi_ao_base + + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); + reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); + reg_val |= sec_con_val; + reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); + writel(reg_val, common->smi_ao_base + + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); + } + + /* gen 2 part */ + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) + writel_relaxed(larbostd[i], + larb->base + SMI_LARB_OSTDL_PORTx(i)); + + /* some gen 0 SoCs need BW calibration */ + if (MTK_SMI_CAPS(larb_gen->flags_general, MTK_SMI_FLAG_BW_CALIBRATE)) { + reg_val = readl_relaxed(larb->base + SMI_LARB_STAT); + if (!reg_val) { + writel_relaxed(0xffffffff, + larb->base + SMI_LARB_BWFILTER_EN); + + ret = readl_poll_timeout( + larb->base + SMI_LARB_FIFO_STAT0, tmp, + tmp == 0xaaaa, 500, 64 * 500); + if (ret) + dev_warn(dev, + "BW limiter calibration timeout\n"); + + writel_relaxed(0, larb->base + SMI_LARB_BWFILTER_EN); + writel_relaxed(0xffffffff, + larb->base + SMI_LARB_OSTD_CTRL_EN); + } + } + + return 0; +} + static int mtk_smi_larb_config_port_gen1(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); From 712249221c3e2202105383e9b6d2887fe546f2f5 Mon Sep 17 00:00:00 2001 From: rva3 Date: Wed, 4 Mar 2026 03:59:13 +0200 Subject: [PATCH 14/69] memory: mtk-smi: add mt6572 larb support Add platform data for the mt6572 SoC. Signed-off-by: rva3 --- drivers/memory/mtk-smi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index d3762a0e499bc1..0866ca5d17c2e5 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -352,6 +352,11 @@ static int mtk_smi_larb_config_port_gen2_general(struct device *dev) return 0; } +static const u8 mtk_smi_larb_mt6572_ostd[][SMI_LARB_PORT_NR_MAX] = { + [0] = {0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, + 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f}, +}; + static const u8 mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = { [0] = {0x2, 0x6, 0x2, 0x2, 0x2, 0x28, 0x18, 0x18, 0x1, 0x1, 0x1, 0x8, 0x8, 0x1, 0x3f}, @@ -560,6 +565,14 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt6572 = { + /* larb0 has 16 ports */ + .port_in_larb = { 0, 16 }, + .config_port = mtk_smi_larb_config_port_gen0, + .flags_general = MTK_SMI_FLAG_BW_CALIBRATE, + .ostd = mtk_smi_larb_mt6572_ostd, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { .config_port = mtk_smi_larb_config_port_gen2_general, .larb_direct_to_common_mask = @@ -617,6 +630,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, + {.compatible = "mediatek,mt6572-smi-larb", .data = &mtk_smi_larb_mt6572}, {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173}, {.compatible = "mediatek,mt6893-smi-larb", .data = &mtk_smi_larb_mt6893}, From ff4227fa58169f4a87e37ba45d9f8fe64b6957b9 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Mar 2026 04:43:43 +0200 Subject: [PATCH 15/69] iommu: mtk_iommu_v1: add mt65xx support The mt65xx SoC family utilizes an earlier version of the IOMMU which shares the same v1 architecture but has minor hardware differences compared to mt2701. Introduce mtk_iommu_type to distinguish between mt2701 and mt65xx variants and apply the necessary logic. Signed-off-by: rva3 --- drivers/iommu/mtk_iommu_v1.c | 67 +++++++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index ac97dd2868d4b8..1a8fb39e50995f 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -85,6 +85,13 @@ struct dma_iommu_mapping { #define F_DESC_NONSEC BIT(3) #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) + +#define MT65XX_MMU_INT_ID_PORT_ID GENMASK(12, 8) +#define MT65XX_MMU_INT_ID_LARB_ID GENMASK(14, 13) + +#define MT65XX_M4U_TF_PORT(TF) FIELD_GET(MT65XX_MMU_INT_ID_PORT_ID, TF) +#define MT65XX_M4U_TF_LARB(TF) (FIELD_GET(MT65XX_MMU_INT_ID_LARB_ID, TF) - 1) + /* MTK generation one iommu HW only support 4K size mapping */ #define MT2701_IOMMU_PAGE_SHIFT 12 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) @@ -96,6 +103,11 @@ struct dma_iommu_mapping { */ #define M2701_IOMMU_PGT_SIZE SZ_4M +enum mtk_iommu_type { + MTK_IOMMU_MT65XX, + MTK_IOMMU_V1, +}; + struct mtk_iommu_v1_suspend_reg { u32 standard_axi_mode; u32 dcm_dis; @@ -116,6 +128,8 @@ struct mtk_iommu_v1_data { struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; struct mtk_iommu_v1_suspend_reg reg; + + enum mtk_iommu_type type; }; struct mtk_iommu_v1_domain { @@ -170,8 +184,11 @@ static inline int mt2701_m4u_to_port(int id) static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data) { - writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + REG_MMU_INV_SEL); + u32 val = F_INVLD_EN0; + if (data->type == MTK_IOMMU_V1) + val |= F_INVLD_EN1; + + writel_relaxed(val, data->base + REG_MMU_INV_SEL); writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); wmb(); /* Make sure the tlb flush all done */ } @@ -180,25 +197,31 @@ static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data, unsigned long iova, size_t size) { int ret; - u32 tmp; + u32 tmp, val = F_INVLD_EN0; + if (data->type == MTK_IOMMU_V1) + val |= F_INVLD_EN1; - writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, - data->base + REG_MMU_INV_SEL); + writel_relaxed(val, data->base + REG_MMU_INV_SEL); writel_relaxed(iova & F_MMU_FAULT_VA_MSK, data->base + REG_MMU_INVLD_START_A); writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, data->base + REG_MMU_INVLD_END_A); writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); - ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, - tmp, tmp != 0, 10, 100000); - if (ret) { - dev_warn(data->dev, - "Partial TLB flush timed out, falling back to full flush\n"); - mtk_iommu_v1_tlb_flush_all(data); + if (data->type == MTK_IOMMU_V1) { + ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, + tmp, tmp != 0, 10, 100000); + if (ret) { + dev_warn(data->dev, + "Partial TLB flush timed out, falling back to full flush\n"); + mtk_iommu_v1_tlb_flush_all(data); + } + + /* Clear the CPE status */ + writel_relaxed(0, data->base + REG_MMU_CPE_DONE); + } else { + wmb(); } - /* Clear the CPE status */ - writel_relaxed(0, data->base + REG_MMU_CPE_DONE); } static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) @@ -215,8 +238,14 @@ static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) fault_iova &= F_MMU_FAULT_VA_MSK; fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); regval = readl_relaxed(data->base + REG_MMU_INT_ID); - fault_larb = MT2701_M4U_TF_LARB(regval); - fault_port = MT2701_M4U_TF_PORT(regval); + + if (data->type == MTK_IOMMU_V1) { + fault_larb = MT2701_M4U_TF_LARB(regval); + fault_port = MT2701_M4U_TF_PORT(regval); + } else { + fault_larb = MT65XX_M4U_TF_LARB(regval); + fault_port = MT65XX_M4U_TF_PORT(regval); + } /* * MTK v1 iommu HW could not determine whether the fault is read or @@ -548,7 +577,10 @@ static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) return ret; } - regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); + regval = F_MMU_TF_PROTECT_SEL(2); + if (data->type == MTK_IOMMU_V1) + regval |= F_MMU_CTRL_COHERENT_EN; + writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); regval = F_INT_TRANSLATION_FAULT | @@ -596,7 +628,7 @@ static const struct iommu_ops mtk_iommu_v1_ops = { }; static const struct of_device_id mtk_iommu_v1_of_ids[] = { - { .compatible = "mediatek,mt2701-m4u", }, + { .compatible = "mediatek,mt2701-m4u", .data = (void *)MTK_IOMMU_V1 }, {} }; MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids); @@ -620,6 +652,7 @@ static int mtk_iommu_v1_probe(struct platform_device *pdev) return -ENOMEM; data->dev = dev; + data->type = (enum mtk_iommu_type)of_device_get_match_data(dev); /* Protect memory. HW will access here while translation fault.*/ protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, From 4a62973f8c900ec18c4ac4c742f2ae5e322b86c0 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Mar 2026 04:44:40 +0200 Subject: [PATCH 16/69] iommu: mtk_iommu_v1: add support for mt6572 Add platform data for the mt6572 SoC. Signed-off-by: rva3 --- drivers/iommu/mtk_iommu_v1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index 1a8fb39e50995f..16f99015797cbd 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -629,6 +629,7 @@ static const struct iommu_ops mtk_iommu_v1_ops = { static const struct of_device_id mtk_iommu_v1_of_ids[] = { { .compatible = "mediatek,mt2701-m4u", .data = (void *)MTK_IOMMU_V1 }, + { .compatible = "mediatek,mt6572-m4u", .data = (void *)MTK_IOMMU_MT65XX }, {} }; MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids); From b3cf0a5737cce9fdc594f375205cc325fa813282 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 6 Feb 2026 21:23:44 +0200 Subject: [PATCH 17/69] soc: mediatek: pwrap: add mt6572 support Signed-off-by: rva3 --- drivers/soc/mediatek/mtk-pmic-wrap.c | 116 +++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 0bcd8582637550..1426262e8d48b1 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -3,6 +3,7 @@ * Copyright (c) 2014 MediaTek Inc. * Author: Flora Fu, MediaTek */ + #include #include #include @@ -569,6 +570,96 @@ static const int mt2701_regs[] = { [PWRAP_ADC_RDATA_ADDR2] = 0x154, }; +static const int mt6572_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_OP_TYPE] = 0x10, + [PWRAP_MSB_FIRST] = 0x14, + [PWRAP_RDDMY] = 0x18, + [PWRAP_SI_CK_CON] = 0x1c, + [PWRAP_CSHEXT_WRITE] = 0x20, + [PWRAP_CSHEXT_READ] = 0x24, + [PWRAP_CSLEXT_START] = 0x28, + [PWRAP_CSLEXT_END] = 0x2c, + [PWRAP_STAUPD_PRD] = 0x30, + [PWRAP_STAUPD_GRPEN] = 0x34, + [PWRAP_STAUPD_MAN_TRIG] = 0x38, + [PWRAP_STAUPD_STA] = 0x3c, + [PWRAP_GPS_STA] = 0x40, + [PWRAP_WRAP_STA] = 0x44, + [PWRAP_HARB_INIT] = 0x48, + [PWRAP_HARB_HPRIO] = 0x4c, + [PWRAP_HIPRIO_ARB_EN] = 0x50, + [PWRAP_HARB_STA0] = 0x54, + [PWRAP_HARB_STA1] = 0x58, + [PWRAP_MAN_EN] = 0x5c, + [PWRAP_MAN_CMD] = 0x60, + [PWRAP_MAN_RDATA] = 0x64, + [PWRAP_MAN_VLDCLR] = 0x68, + [PWRAP_WACS0_EN] = 0x6c, + [PWRAP_INIT_DONE0] = 0x70, + [PWRAP_WACS0_CMD] = 0x74, + [PWRAP_WACS0_RDATA] = 0x78, + [PWRAP_WACS0_VLDCLR] = 0x7c, + [PWRAP_WACS1_EN] = 0x80, + [PWRAP_INIT_DONE1] = 0x84, + [PWRAP_WACS1_CMD] = 0x88, + [PWRAP_WACS1_RDATA] = 0x8c, + [PWRAP_WACS1_VLDCLR] = 0x90, + [PWRAP_WACS2_EN] = 0x94, + [PWRAP_INIT_DONE2] = 0x98, + [PWRAP_WACS2_CMD] = 0x9c, + [PWRAP_WACS2_RDATA] = 0xa0, + [PWRAP_WACS2_VLDCLR] = 0xa4, + [PWRAP_INT_EN] = 0xa8, + [PWRAP_INT_FLG_RAW] = 0xac, + [PWRAP_INT_FLG] = 0xb0, + [PWRAP_INT_CLR] = 0xb4, + [PWRAP_SIG_ADR] = 0xb8, + [PWRAP_SIG_MODE] = 0xbc, + [PWRAP_SIG_VALUE] = 0xc0, + [PWRAP_SIG_ERRVAL] = 0xc4, + [PWRAP_CRC_EN] = 0xc8, + [PWRAP_TIMER_EN] = 0xcc, + [PWRAP_TIMER_STA] = 0xd0, + [PWRAP_WDT_UNIT] = 0xd4, + [PWRAP_WDT_SRC_EN] = 0xd8, + [PWRAP_WDT_FLG] = 0xdc, + [PWRAP_DEBUG_INT_SEL] = 0xe0, + [PWRAP_DVFS_ADR0] = 0xe4, + [PWRAP_DVFS_WDATA0] = 0xe8, + [PWRAP_DVFS_ADR1] = 0xec, + [PWRAP_DVFS_WDATA1] = 0xf0, + [PWRAP_DVFS_ADR2] = 0xf4, + [PWRAP_DVFS_WDATA2] = 0xf8, + [PWRAP_DVFS_ADR3] = 0xfc, + [PWRAP_DVFS_WDATA3] = 0x100, + [PWRAP_DVFS_ADR4] = 0x104, + [PWRAP_DVFS_WDATA4] = 0x108, + [PWRAP_DVFS_ADR5] = 0x10c, + [PWRAP_DVFS_WDATA5] = 0x110, + [PWRAP_DVFS_ADR6] = 0x114, + [PWRAP_DVFS_WDATA6] = 0x118, + [PWRAP_DVFS_ADR7] = 0x11c, + [PWRAP_DVFS_WDATA7] = 0x120, + [PWRAP_CIPHER_KEY_SEL] = 0x124, + [PWRAP_CIPHER_IV_SEL] = 0x128, + [PWRAP_CIPHER_EN] = 0x12c, + [PWRAP_CIPHER_RDY] = 0x130, + [PWRAP_CIPHER_MODE] = 0x134, + [PWRAP_CIPHER_SWRST] = 0x138, + [PWRAP_DCM_EN] = 0x13c, + [PWRAP_DCM_DBC_PRD] = 0x140, + [PWRAP_ADC_CMD_ADDR] = 0x144, + [PWRAP_PWRAP_ADC_CMD] = 0x148, + [PWRAP_ADC_RDY_ADDR] = 0x14c, + [PWRAP_ADC_RDATA_ADDR1] = 0x150, + [PWRAP_ADC_RDATA_ADDR2] = 0x154, + [PWRAP_SW_RST] = 0x180, +}; + static const int mt6765_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1314,6 +1405,7 @@ enum pmic_type { enum pwrap_type { PWRAP_MT2701, + PWRAP_MT6572, PWRAP_MT6765, PWRAP_MT6779, PWRAP_MT6795, @@ -1733,6 +1825,11 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6572: + pwrap_writel(wrp, 0x8, PWRAP_RDDMY); + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + pwrap_init_chip_select_ext(wrp, 5, 0, 0, 0); + break; case PWRAP_MT6795: if (wrp->slave->type == PMIC_MT6331) { const u32 *dew_regs = wrp->slave->dew_regs; @@ -1839,6 +1936,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_CIPHER_START); break; case PWRAP_MT2701: + case PWRAP_MT6572: case PWRAP_MT6765: case PWRAP_MT6779: case PWRAP_MT6795: @@ -2061,6 +2159,10 @@ static int pwrap_init(struct pmic_wrapper *wrp) reset_control_reset(wrp->rstc_bridge); switch (wrp->master->type) { + case PWRAP_MT6572: + pwrap_writel(wrp, 1, PWRAP_DCM_EN); + pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); + break; case PWRAP_MT6795: fallthrough; case PWRAP_MT8173: @@ -2277,6 +2379,19 @@ static const struct pmic_wrapper_type pwrap_mt2701 = { .init_soc_specific = pwrap_mt2701_init_soc_specific, }; +static const struct pmic_wrapper_type pwrap_mt6572 = { + .regs = mt6572_regs, + .type = PWRAP_MT6572, + .arb_en_all = 0x1ff, + .int_en_all = 0x7ffffffd, + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + //.caps = /*PWRAP_CAP_RESET |*/ PWRAP_CAP_DCM, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt2701_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6765 = { .regs = mt6765_regs, .type = PWRAP_MT6765, @@ -2446,6 +2561,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = { static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, + { .compatible = "mediatek,mt6572-pwrap", .data = &pwrap_mt6572 }, { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, From 603809c4357ecd41d617bb237a053792230c2262 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:18:27 +0200 Subject: [PATCH 18/69] soc: mediatek: mmsys: add mt6572 support XXX: fixme Signed-off-by: rva3 --- drivers/soc/mediatek/mt6572-mmsys.h | 31 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++ 2 files changed, 39 insertions(+) create mode 100644 drivers/soc/mediatek/mt6572-mmsys.h diff --git a/drivers/soc/mediatek/mt6572-mmsys.h b/drivers/soc/mediatek/mt6572-mmsys.h new file mode 100644 index 00000000000000..31daa1d6d2290d --- /dev/null +++ b/drivers/soc/mediatek/mt6572-mmsys.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026 rva3 + */ + +#ifndef __SOC_MEDIATEK_MT6572_MMSYS_H +#define __SOC_MEDIATEK_MT6572_MMSYS_H + +static const struct mtk_mmsys_routes mt6572_mmsys_routing_table[] = { + /* ovl0 goes to rdma0 */ + MMSYS_ROUTE(OVL0, RDMA0, 0x030, BIT(0), BIT(0)), + + /* rdma0 goes to color0 */ + MMSYS_ROUTE(RDMA0, COLOR0, 0x050, BIT(0), 0), + MMSYS_ROUTE(RDMA0, COLOR0, 0x054, BIT(0), 0), + + /* XXX: BLS, not aal... */ + MMSYS_ROUTE(AAL0, DSI0, 0x058, BIT(0), 0), + MMSYS_ROUTE(AAL0, DSI0, 0x04C, 0x3, 0), + + /* ?????? */ + MMSYS_ROUTE(RDMA0, DSI0, 0x050, BIT(0), BIT(0)), + MMSYS_ROUTE(RDMA0, DSI0, 0x058, BIT(0), BIT(0)), + MMSYS_ROUTE(RDMA0, DSI0, 0x04C, 0x3, 0), + + /* ???????????????????????? */ + MMSYS_ROUTE(OVL0, COLOR0, 0x030, BIT(2), BIT(2)), + MMSYS_ROUTE(OVL0, COLOR0, 0x054, BIT(0), BIT(0)), +}; + +#endif /* __SOC_MEDIATEK_MT6572_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index bb4639ca0b8cdc..87e7b9b3e3dbec 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -14,6 +14,7 @@ #include #include "mtk-mmsys.h" +#include "mt6572-mmsys.h" #include "mt8167-mmsys.h" #include "mt8173-mmsys.h" #include "mt8183-mmsys.h" @@ -37,6 +38,12 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; +static const struct mtk_mmsys_driver_data mt6572_mmsys_driver_data = { + .clk_driver = "clk-mt6572-mm", + .routes = mt6572_mmsys_routing_table, + .num_routes = ARRAY_SIZE(mt6572_mmsys_routing_table), +}; + static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", }; @@ -458,6 +465,7 @@ static void mtk_mmsys_remove(struct platform_device *pdev) static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data }, { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data }, + { .compatible = "mediatek,mt6572-mmsys", .data = &mt6572_mmsys_driver_data }, { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data }, { .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data }, { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data }, From 224444cb531a2c0e49e81b56dc0e37f4196a276a Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:43:04 +0200 Subject: [PATCH 19/69] soc: mediatek: mtk-mutex: add mt6572 support Add platform data for the mt6572 SoC. Signed-off-by: rva3 --- drivers/soc/mediatek/mtk-mutex.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 38179e8cd98f84..2f96decd90d751 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -330,6 +330,13 @@ #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) +#define MT6572_MUTEX_MOD_DISP_OVL 3 +#define MT6572_MUTEX_MOD_DISP_WDMA 6 +#define MT6572_MUTEX_MOD_DISP_COLOR 7 +#define MT6572_MUTEX_MOD_DISP_BLS 9 +// XXX: this is RDMA1, RDMA0 is MDP +#define MT6572_MUTEX_MOD_DISP_RDMA0 10 + struct mtk_mutex { u8 id; bool claimed; @@ -397,6 +404,14 @@ static const u8 mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; +static const u8 mt6572_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT6572_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT6572_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT6572_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT6572_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_WDMA0] = MT6572_MUTEX_MOD_DISP_WDMA, +}; + static const u8 mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, @@ -746,6 +761,13 @@ static const struct mtk_mutex_data mt2712_mutex_driver_data = { .mutex_sof_reg = MT2701_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt6572_mutex_driver_data = { + .mutex_mod = mt6572_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, +}; + static const struct mtk_mutex_data mt6795_mutex_driver_data = { .mutex_mod = mt8173_mutex_mod, .mutex_sof = mt6795_mutex_sof, @@ -1132,6 +1154,7 @@ static int mtk_mutex_probe(struct platform_device *pdev) static const struct of_device_id mutex_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data }, { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data }, + { .compatible = "mediatek,mt6572-disp-mutex", .data = &mt6572_mutex_driver_data }, { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data }, { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data }, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data }, From b394dd5e3fbca9cdf69eacde456cb91055821702 Mon Sep 17 00:00:00 2001 From: rva3 Date: Wed, 11 Mar 2026 15:04:46 +0200 Subject: [PATCH 20/69] drm: mediatek: ovl: attach errors for the interrupt XXX: maybe we should drop this?.. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 ++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index e0236353d4997e..32cee6f4c9e9d4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -20,9 +20,21 @@ #include "mtk_disp_drv.h" #include "mtk_drm_drv.h" -#define DISP_REG_OVL_INTEN 0x0004 -#define OVL_FME_CPL_INT BIT(1) +#define DISP_REG_OVL_INTEN 0x0004 +#define OVL_FME_CPL_INT BIT(1) +#define OVL_FME_UND_INT BIT(2) +#define OVL_RDMA0_EOF_ABNORMAL_INT BIT(5) +#define OVL_RDMA1_EOF_ABNORMAL_INT BIT(6) +#define OVL_RDMA0_FIFO_UND_INT BIT(9) +#define OVL_RDMA1_FIFO_UND_INT BIT(10) + #define DISP_REG_OVL_INTSTA 0x0008 +#define OVL_FME_UND BIT(2) +#define OVL_RDMA0_EOF_ABNORMAL BIT(5) +#define OVL_RDMA1_EOF_ABNORMAL BIT(6) +#define OVL_RDMA0_FIFO_UND BIT(9) +#define OVL_RDMA1_FIFO_UND BIT(10) + #define DISP_REG_OVL_EN 0x000c #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 @@ -170,6 +182,18 @@ struct mtk_disp_ovl { static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv = dev_id; + u32 reg = readl(priv->regs + DISP_REG_OVL_INTSTA); + + if (reg & OVL_FME_UND) + pr_err("OVL: OVL frame underflow\n"); + if (reg & OVL_RDMA0_EOF_ABNORMAL) + pr_err("OVL: RDMA0 didn't complete frame\n"); + if (reg & OVL_RDMA1_EOF_ABNORMAL) + pr_err("OVL: RDMA1 didn't complete frame\n"); + if (reg & OVL_RDMA0_FIFO_UND) + pr_err("OVL: RDMA0 FIFO underflow\n"); + if (reg & OVL_RDMA1_FIFO_UND) + pr_err("OVL: RDMA1 FIFO underflow\n"); /* Clear frame completion interrupt */ writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); @@ -205,7 +229,10 @@ void mtk_ovl_enable_vblank(struct device *dev) struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); - writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); + writel_relaxed(OVL_FME_CPL_INT | OVL_FME_UND_INT | + OVL_RDMA0_EOF_ABNORMAL_INT | OVL_RDMA1_EOF_ABNORMAL_INT | + OVL_RDMA0_FIFO_UND_INT | OVL_RDMA1_FIFO_UND_INT, + ovl->regs + DISP_REG_OVL_INTEN); } void mtk_ovl_disable_vblank(struct device *dev) From 81c88d334c74ec6af08b9e7ceade1987696b5790 Mon Sep 17 00:00:00 2001 From: rva3 Date: Wed, 11 Mar 2026 13:57:41 +0200 Subject: [PATCH 21/69] drm: mediatek: ovl: add mt6572 support Add platform data for the mt6572 SoC. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 32cee6f4c9e9d4..5ac8e9b907dba9 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -698,6 +698,19 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), }; +static const struct mtk_disp_ovl_data mt6572_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT2701, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = false, + .supports_afbc = false, + .blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), +}; + static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 8, @@ -769,6 +782,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, + { .compatible = "mediatek,mt6572-disp-ovl", + .data = &mt6572_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl", From 16573da53f4f8ee0e4faf3ae4503eaecc0568ba3 Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:47:01 +0200 Subject: [PATCH 22/69] drm: mediatek: disp_rdma: move size_con0 and size_con1 to platform data The RDMA SIZE_CON0 and SIZE_CON1 values vary across different SoCs. Prepare for supporting new SoCs by moving these values into the mtk_disp_rdma_data and updating existing SoC data to use their respective values. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index c9d41d75e7f2a3..d4038842089f62 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -72,6 +72,8 @@ struct mtk_disp_rdma_data { unsigned int fifo_size; const u32 *formats; size_t num_formats; + u32 size_con0; + u32 size_con1; }; /* @@ -191,9 +193,9 @@ void mtk_rdma_config(struct device *dev, unsigned int width, u32 rdma_fifo_size; mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, - DISP_REG_RDMA_SIZE_CON_0, 0xfff); + DISP_REG_RDMA_SIZE_CON_0, rdma->data->size_con0); mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, - DISP_REG_RDMA_SIZE_CON_1, 0xfffff); + DISP_REG_RDMA_SIZE_CON_1, rdma->data->size_con1); if (rdma->fifo_size) rdma_fifo_size = rdma->fifo_size; @@ -380,24 +382,32 @@ static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { .fifo_size = SZ_4K, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), + .size_con0 = 0xfff, + .size_con1 = 0xfffff, }; static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), + .size_con0 = 0xfff, + .size_con1 = 0xfffff, }; static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), + .size_con0 = 0xfff, + .size_con1 = 0xfffff, }; static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { .fifo_size = 1920, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), + .size_con0 = 0xfff, + .size_con1 = 0xfffff, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { From 6631961b8cbc5ccd5bcedaef107e2c031e2108f4 Mon Sep 17 00:00:00 2001 From: rva3 Date: Sun, 22 Mar 2026 13:29:54 +0200 Subject: [PATCH 23/69] drm: mediatek: disp_rdma: use function pointer for the fmt_convert The RDMA uses different values for memory formats. Currently, these are hardcoded using macros. Move the format conversion logic into function pointer instead of raw call. This allows other SoCs to provide their own mapping logic without breaking others. Also drop useless parameter in the rdma_fmt_convert method. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 50 ++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index d4038842089f62..12460b80c69106 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -36,6 +36,10 @@ #define DISP_REG_RDMA_SIZE_CON_1 0x0018 #define DISP_REG_RDMA_TARGET_LINE 0x001c #define DISP_RDMA_MEM_CON 0x0024 + +#define MEM_MODE_INPUT_FORMAT_RGB565_MT65XX (0x004 << 4) +#define MEM_MODE_INPUT_FORMAT_RGB888_MT65XX (0x008 << 4) + #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4) #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) @@ -74,6 +78,7 @@ struct mtk_disp_rdma_data { size_t num_formats; u32 size_con0; u32 size_con1; + unsigned int (*fmt_convert)(unsigned int fmt); }; /* @@ -215,8 +220,43 @@ void mtk_rdma_config(struct device *dev, unsigned int width, mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); } -static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, - unsigned int fmt) +static unsigned int rdma_fmt_convert_mt65xx(unsigned int fmt) +{ + /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" + * is defined in mediatek HW data sheet. + * The alphabet order in XXX is no relation to data + * arrangement in memory. + */ + switch (fmt) { + default: + case DRM_FORMAT_RGB565: + return MEM_MODE_INPUT_FORMAT_RGB565_MT65XX; + case DRM_FORMAT_BGR565: + return MEM_MODE_INPUT_FORMAT_RGB565_MT65XX | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_RGB888: + return MEM_MODE_INPUT_FORMAT_RGB888_MT65XX; + case DRM_FORMAT_BGR888: + return MEM_MODE_INPUT_FORMAT_RGB888_MT65XX | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + return MEM_MODE_INPUT_FORMAT_ARGB8888; + case DRM_FORMAT_BGRX8888: + case DRM_FORMAT_BGRA8888: + return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + return MEM_MODE_INPUT_FORMAT_RGBA8888; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; + case DRM_FORMAT_UYVY: + return MEM_MODE_INPUT_FORMAT_UYVY; + case DRM_FORMAT_YUYV: + return MEM_MODE_INPUT_FORMAT_YUYV; + } +} + +static unsigned int rdma_fmt_convert(unsigned int fmt) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -268,7 +308,7 @@ void mtk_rdma_layer_config(struct device *dev, unsigned int idx, unsigned int fmt = pending->format; unsigned int con; - con = rdma_fmt_convert(rdma, fmt); + con = rdma->data->fmt_convert(fmt); mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON); if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { @@ -384,6 +424,7 @@ static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), .size_con0 = 0xfff, .size_con1 = 0xfffff, + .fmt_convert = rdma_fmt_convert, }; static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { @@ -392,6 +433,7 @@ static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), .size_con0 = 0xfff, .size_con1 = 0xfffff, + .fmt_convert = rdma_fmt_convert, }; static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { @@ -400,6 +442,7 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), .size_con0 = 0xfff, .size_con1 = 0xfffff, + .fmt_convert = rdma_fmt_convert, }; static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { @@ -408,6 +451,7 @@ static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), .size_con0 = 0xfff, .size_con1 = 0xfffff, + .fmt_convert = rdma_fmt_convert, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { From 768f85b0f607a7b59b4fbb8f78fe1768513e8d06 Mon Sep 17 00:00:00 2001 From: rva3 Date: Sun, 22 Mar 2026 12:43:38 +0200 Subject: [PATCH 24/69] drm: mediatek: disp_rdma: add mt6572 support Add support for the display RDMA in the mt6572 SoC. This requires setting size_con0 and size_con1 registers to zero, unlike other SoCs. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 12460b80c69106..691978d4f1cb83 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -427,6 +427,15 @@ static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { .fmt_convert = rdma_fmt_convert, }; +static const struct mtk_disp_rdma_data mt6572_rdma_driver_data = { + .fifo_size = 3840, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), + .size_con0 = 0, + .size_con1 = 0, + .fmt_convert = rdma_fmt_convert_mt65xx, +}; + static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, .formats = mt8173_formats, @@ -457,6 +466,8 @@ static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, + { .compatible = "mediatek,mt6572-disp-rdma", + .data = &mt6572_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", From 3f0382b895cb15ef07751b24e6882e794041f704 Mon Sep 17 00:00:00 2001 From: rva3 Date: Wed, 11 Mar 2026 19:41:40 +0200 Subject: [PATCH 25/69] drm: mediatek: dsi: add mt6572 support Add platform data for the mt6572 SoC. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index aaf6c9ebd319f7..323532fde0af55 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1278,6 +1278,13 @@ static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { .reg_shadow_dbg_off = 0x190 }; +static const struct mtk_dsi_driver_data mt6572_dsi_driver_data = { + .reg_cmdq_off = 0x180, + .reg_vm_cmd_off = 0x130, + .has_shadow_ctl = false, + .has_size_ctl = false, +}; + static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { .reg_cmdq_off = 0x200, .reg_vm_cmd_off = 0x130, @@ -1306,6 +1313,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { static const struct of_device_id mtk_dsi_of_match[] = { { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data }, + { .compatible = "mediatek,mt6572-dsi", .data = &mt6572_dsi_driver_data }, { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data }, { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data }, { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data }, From 861904e6446454f2d85eb13cc7a575e39c6c6b0d Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:48:49 +0200 Subject: [PATCH 26/69] drm: mediatek: mtk_drm_drv: add mt6572 drm support Add platform data for the mt6572 SoC. Signed-off-by: rva3 --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a94c51a8326162..6ad1be86019ce2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -333,6 +333,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt6572-mmsys", + .data = &mt2701_mmsys_driver_data}, { .compatible = "mediatek,mt7623-mmsys", .data = &mt7623_mmsys_driver_data}, { .compatible = "mediatek,mt2712-mmsys", @@ -752,6 +754,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt6572-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8167-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", @@ -772,6 +776,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt6572-disp-ovl", + .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8167-disp-ovl", .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", @@ -796,6 +802,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt6572-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8167-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", @@ -828,6 +836,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt6572-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8183-dsi", From 9cf9dcb61378fb032a39910a736f9fcbef92bbed Mon Sep 17 00:00:00 2001 From: rva3 Date: Fri, 13 Mar 2026 13:28:41 +0200 Subject: [PATCH 27/69] drm: panel: add wsvgalnl ek79007 panel support Signed-off-by: rva3 --- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-wsvgalnl-ek79007.c | 259 ++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-wsvgalnl-ek79007.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 307152ad77591a..86243226fc7e2e 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -1214,6 +1214,15 @@ config DRM_PANEL_WIDECHIPS_WS2401 480x800 display controller used in panels such as Samsung LMS380KF01. This display is used in the Samsung Galaxy Ace 2 GT-I8160 (Codina). +config DRM_PANEL_WSVGALNL_EK79007 + tristate "WSVGALNL EK79007 DSI panel driver" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the WSVGALNL EK79007 DSI + 1024x600 LCD panel + config DRM_PANEL_XINPENG_XPP055C272 tristate "Xinpeng XPP055C272 panel driver" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index aeffaa95666d6d..70f9a8e77765d4 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -120,4 +120,5 @@ obj-$(CONFIG_DRM_PANEL_VISIONOX_RM692E5) += panel-visionox-rm692e5.o obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o +obj-$(CONFIG_DRM_PANEL_WSVGALNL_EK79007) += panel-wsvgalnl-ek79007.o obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o diff --git a/drivers/gpu/drm/panel/panel-wsvgalnl-ek79007.c b/drivers/gpu/drm/panel/panel-wsvgalnl-ek79007.c new file mode 100644 index 00000000000000..b91ae778c2a3ad --- /dev/null +++ b/drivers/gpu/drm/panel/panel-wsvgalnl-ek79007.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include + +#include