FPGA_Hack/.gitignore at main · StackedArchitect/FPGA_Hack · GitHub

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# Python
__pycache__/
*.pyc
*.pyo
.venv/
*.egg-info/

# Jupyter
.ipynb_checkpoints/

# Dataset files (download via main.py --download)
software/data/

# Trained models (regenerated by training)
software/models/*.pth

# Results images (regenerated by evaluate)
software/results/*.png

# FPGA export files (regenerated by --export)
hardware/tb/test_vectors/*.mem
hardware/tb/test_vectors/*.hex
hardware/tb/test_vectors/*.coe

# Vivado project files (regenerated by create_project.tcl)
hardware/vivado/*.xpr
hardware/vivado/*.runs/
hardware/vivado/*.srcs/
hardware/vivado/*.cache/
hardware/vivado/*.hw/
hardware/vivado/*.ip_user_files/
hardware/vivado/*.sim/
hardware/vivado/NA/
hardware/tb/test_vectors/*.vh

# Vivado generated files
hardware/vivado/hdc_amc/
*.jou
*.log
*.str
*.bit
*.bin
*.ltx

# Simulation artifacts
*.vcd
hardware/tb/tb_wav
hardware/tb/tb_wavebnn
hardware/tb/sim_wavelet
hardware/tb/tb_debug
hardware/tb/tb_sys_sv
hardware/tb/test_vectors/tb_*

# OS
.DS_Store
Thumbs.db

# IDE
.vscode/
*.swp
*.swo

# Gemini artifacts
.gemini/