mm_stdlib.py

from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_private_l2 import PrivateL1PrivateL2
from gem5.components.memory.single_channel import (
    SingleChannelDDR3_1600, SingleChannelDDR4_2400, SingleChannelDDR5_4400
)
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.isas import ISA
from gem5.resources.resource import CustomResource
from gem5.simulate.simulator import Simulator
import os
CPU_TYPE = os.environ.get("CPU_TYPE", "TIMING").upper()   # ATOMIC | TIMING | O3 | MINOR
CLK_FREQ = os.environ.get("CLK_FREQ", "2GHz")
MEM_TYPE = os.environ.get("MEM_TYPE", "DDR3")             # DDR3 | DDR4 | DDR5
L1I = os.environ.get("L1I", "32kB")
L1D = os.environ.get("L1D", "32kB")
L2  = os.environ.get("L2",  "1MB")
BIN = os.environ.get("BIN", "/tmp/mm.aarch64")
N   = os.environ.get("N", "192")  # matrix size
if MEM_TYPE == "DDR3":
    memory = SingleChannelDDR3_1600(size="1GB")
elif MEM_TYPE == "DDR4":
    memory = SingleChannelDDR4_2400(size="1GB")
elif MEM_TYPE == "DDR5":
    memory = SingleChannelDDR5_4400(size="1GB")
else:
    raise ValueError(f"Unknown MEM_TYPE {MEM_TYPE}")
cache_hierarchy = PrivateL1PrivateL2(
    l1i_size=L1I, l1i_assoc=8,
    l1d_size=L1D, l1d_assoc=8,
    l2_size=L2,   l2_assoc=16,
)
cpu_map = {
    "ATOMIC": CPUTypes.ATOMIC,
    "TIMING": CPUTypes.TIMING,
    "O3":     CPUTypes.O3,
    "MINOR":  CPUTypes.MINOR,
}
if CPU_TYPE not in cpu_map:
    raise ValueError(f"Unknown CPU_TYPE {CPU_TYPE}")
processor = SimpleProcessor(cpu_type=cpu_map[CPU_TYPE], isa=ISA.ARM, num_cores=1)
board = SimpleBoard(
    clk_freq=CLK_FREQ,
    processor=processor,
    memory=memory,
    cache_hierarchy=cache_hierarchy,
)
board.set_workload(CustomResource(BIN), arguments=[N])
sim = Simulator(board=board)
sim.run()