xrun compilation error

[agrobman]

when it try to compile standalone RTL as :

xrun submodules/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv rtl/verilog/*.sv

I'm getting following error:

  function slave_mask_t invert_slave_mask;
                                        |
xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable datatype.
  function slave_mask_t invert_slave_mask;
                                        |
xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable datatype.
  parameter bit [SLAVES-1:0] ERROR_ON_SLAVE_MASK[MASTERS] = invert_slave_mask(),
                                                                            |
xmvlog: *N,CFCALL (../rtl/verilog/ahb3lite_interconnect.sv,136|76): Function invert_slave_mask treated as a constant function because of this call.
	module worklib.ahb3lite_interconnect:sv

What do I miss?

I use xcellium version 20.03-s003

[rherveille]

The code has been compiled using the Intel, Xilinx, and Lattice design flows.
We run simulations with the Aldec and Mentor tools. Unfortunately I do not have access to the Cadence tools.
It seems like the tool doesn't like/find the type definition. You can try moving the type definition before its use. Or place the type definition in a separate package.

Richard

[pantikov]

Hello!

Fixed the issue with the patch below.

ahb3lite_interconnect.txt

[rherveille]

That fix mixes ANSI-style and old-style (K&R) parameter declarations. That causes problems in other tools.

[martinpriestley]

I see this too.
I suspect Xcelium is trying to resolve the paramlist before the type, and therefore the type is "unavailable" at this point. I'll raise a case with Cadence.

It's not possible to move the move the type definition to a package, as its definition depends on the values of MASTERS and SLAVES.

The best workaround I can come up with is to initialise ERROR_ON_SLAVE_MASK with a non-sane value (like all 1s - who'd want an interconnect where nothing is accessible?), then derive the actual mask as a localparam in the module body.

localparam bit [SLAVES-1:0] ACTUAL_ERROR_ON_SLAVE_MASK[MASTERS] = (ERROR_ON_SLAVE_MASK == '{MASTERS{ {SLAVES{1'b1}} }}) ? invert_slave_mask() : ERROR_ON_SLAVE_MASK;

Xcelium is happy with this, but Verilator doesn't (which I think is a limitation of Verilator: verilator/verilator#2272).

For now I'm just going to move it to be a localparam in the module body, as I don't think I have any need to override ERROR_ON_SLAVE_MASK.

[rherveille]

The Cadence tools are known to be very strict. The code works in all other tools.