alu_tb.v

module alu_tb;

    // inputs as reg (we drive them)
    reg [7:0] A;
    reg [7:0] B;
    reg [2:0] alu_sel;

    // outputs as wire (we observe them)
    wire [7:0] result;
    wire zero;

    // connect testbench to ALU module
    alu uut (
        .A(A),
        .B(B),
        .alu_sel(alu_sel),
        .result(result),
        .zero(zero)
    );

    initial begin
        $dumpfile("dump.vcd");   // for waveform
        $dumpvars(0, alu_tb);

        // Test 1: ADD 15 + 10 = 25
        A = 8'd15; B = 8'd10; alu_sel = 3'b000;
        #10;
        $display("ADD: %0d + %0d = %0d", A, B, result);

        // Test 2: SUB 20 - 5 = 15
        A = 8'd20; B = 8'd5; alu_sel = 3'b001;
        #10;
        $display("SUB: %0d - %0d = %0d", A, B, result);

        // Test 3: AND
        A = 8'b11001100; B = 8'b10101010; alu_sel = 3'b010;
        #10;
        $display("AND: %b & %b = %b", A, B, result);

        // Test 4: OR
        A = 8'b11001100; B = 8'b10101010; alu_sel = 3'b011;
        #10;
        $display("OR:  %b | %b = %b", A, B, result);

        // Test 5: zero flag test (5 - 5 = 0)
        A = 8'd5; B = 8'd5; alu_sel = 3'b001;
        #10;
        $display("SUB: %0d - %0d = %0d | zero flag = %b", A, B, result, zero);

        $finish;
    end

endmodule