RISCVBusiness/.gitignore at a6bdb1f65fb496fca50ca8a18531d7aebebc7b2b · JakeStevens/RISCVBusiness · GitHub

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# ignore the build and run files
build/
sim_out/
obj_dir/
rvb_out/
# ignore memory files from test cases
*.hex
meminit.ver
verification/asm-tests/RV32I/*.elf
verification/asm-tests/RV32I/*.log
verification/asm-tests/RV32I/*.hex
*.bin
*.elf
# config files are auto-generated
source_code/include/component_selection_defines.vh
verification/c-firmware/custom_instruction_calls.h
# proprietary files
source_code/ram/altera_mf.v
source_code/ram/altera_mf.sv
source_code/ram/ram.sv
# backup files
source_code/fpga/*.bak
source_code/fpga/db
source_code/fpga/incremental_db
source_code/fpga/output_files
# Ignore open vim files
*.swp
# Ignore git merge temporary files
*.orig
# Ignore waf lock
*.lock-waf*
# Ignore files for commands for moving stuff around
*.cmd
mitll*
# Ignore temporary files created by gedit
*~
# Ignore test cache files
run_tests_cache.json
# Ignore log files and Verilator outputs
*.log
*.fst
memsim.dump
meminit.bin

# ignore files auto-generated by vscode.
_info
_vmake
*.qdb
*.qtl
*.qpg

# ignore python bytecode files
*.pyc
__pycache__/

# ignore xrun files
INCA_libs/
xcelium.d/
xrun.history
xrun.key
.simvision
waves.shm/

open_files.sh

# fusesoc
fusesoc_libraries
fusesoc.conf

# synthesis scripts
desflow1/
.vscode/

# uvm
work
mapped
fpga
transcript
*.wlf
README
*.swp
._*
*.log
*.deps
*.hex
*.ver
mti*
*.diff
system.summary
system_fpga.summary
*.vstf
*vsim*