Skip to content

Commit 32722e1

Browse files
authored
32-bit zero loop iteration (#2939)
* 32-bit zero loop iteration * fix * fix * fix * fix
1 parent 04b80f6 commit 32722e1

6 files changed

Lines changed: 75 additions & 9 deletions

File tree

enzyme/Enzyme/CacheUtility.cpp

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -725,8 +725,22 @@ bool CacheUtility::getContext(BasicBlock *BB, LoopContext &loopContext,
725725
}
726726
endOMP:;
727727

728-
if (Limit->getType() != CanonicalIV->getType())
729-
Limit = SE.getZeroExtendExpr(Limit, CanonicalIV->getType());
728+
if (Limit->getType() != CanonicalIV->getType()) {
729+
const SCEV *Zero = SE.getZero(Limit->getType());
730+
const Loop *outermost = L;
731+
while (outermost->getParentLoop()) {
732+
outermost = outermost->getParentLoop();
733+
}
734+
BasicBlock *outermostPreheader = outermost->getLoopPreheader();
735+
Instruction *context = outermostPreheader
736+
? outermostPreheader->getTerminator()
737+
: loopContexts[L].preheader->getTerminator();
738+
if (SE.isKnownPredicateAt(ICmpInst::ICMP_SGE, Limit, Zero, context)) {
739+
Limit = SE.getZeroExtendExpr(Limit, CanonicalIV->getType());
740+
} else {
741+
Limit = SE.getSignExtendExpr(Limit, CanonicalIV->getType());
742+
}
743+
}
730744

731745
#if LLVM_VERSION_MAJOR >= 22
732746
SCEVExpander Exp(SE, "enzyme");

enzyme/test/Enzyme/ReverseMode/metasinfor.ll

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -79,10 +79,9 @@ attributes #8 = { noreturn nounwind }
7979
; CHECK-NEXT: store double 0.000000e+00, double* %"a.addr'ipa", align 8
8080
; CHECK-NEXT: %a.addr = alloca double, align 8
8181
; CHECK-NEXT: store double %a, double* %a.addr, align 8, !tbaa !2
82-
; CHECK-NEXT: %0 = zext i32 %n to i64
83-
; CHECK-NEXT: %1 = add {{(nuw nsw )?}}i64 %0, 1
84-
; CHECK-NEXT: br label
85-
; %invertfor.cond
82+
; CHECK-NEXT: %0 = add {{(nuw )?}}i32 %n, 1
83+
; CHECK-NEXT: %1 = sext i32 %0 to i64
84+
; CHECK-NEXT: br label %invertfor.cond
8685

8786
; CHECK: invertentry: ; preds = %invertfor.cond
8887
; CHECK-NEXT: %[[padd:.+]] = load double, double* %"a.addr'ipa", align 8
Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
; RUN: if [ %llvmver -lt 16 ]; then %opt < %s %loadEnzyme -enzyme-preopt=false -enzyme -mem2reg -instsimplify -adce -S | FileCheck %s; fi
2+
; RUN: %opt < %s %newLoadEnzyme -enzyme-preopt=false -passes="enzyme,function(mem2reg,instsimplify,adce)" -S | FileCheck %s
3+
4+
define void @nested(float* %x, i32 %outer, i32 %inner) {
5+
entry:
6+
%cmp.out = icmp slt i32 %outer, 1
7+
br i1 %cmp.out, label %exit, label %outer.preheader
8+
9+
outer.preheader:
10+
br label %outer.loop
11+
12+
outer.loop:
13+
%iv.out = phi i32 [ 1, %outer.preheader ], [ %iv.out.next, %outer.loop.latch ]
14+
15+
; Inner loop guard
16+
%cmp.in = icmp slt i32 %inner, 1
17+
br i1 %cmp.in, label %outer.loop.latch, label %inner.preheader
18+
19+
inner.preheader:
20+
br label %inner.loop
21+
22+
inner.loop:
23+
%iv.in = phi i32 [ 1, %inner.preheader ], [ %iv.in.next, %inner.loop ]
24+
25+
%idx = getelementptr inbounds float, float* %x, i32 %iv.in
26+
%val = load float, float* %idx, align 4
27+
%val2 = fmul float %val, %val
28+
store float %val2, float* %idx, align 4
29+
30+
%iv.in.next = add i32 %iv.in, 1
31+
%cmp.in.loop = icmp eq i32 %iv.in, %inner
32+
br i1 %cmp.in.loop, label %outer.loop.latch, label %inner.loop
33+
34+
outer.loop.latch:
35+
%iv.out.next = add i32 %iv.out, 1
36+
%cmp.out.loop = icmp eq i32 %iv.out, %outer
37+
br i1 %cmp.out.loop, label %exit, label %outer.loop
38+
39+
exit:
40+
ret void
41+
}
42+
43+
declare void @__enzyme_autodiff(i8*, float*, float*, i32, i32)
44+
45+
define void @diffe_nested(float* %x, float* %xp, i32 %outer, i32 %inner) {
46+
entry:
47+
call void @__enzyme_autodiff(i8* bitcast (void (float*, i32, i32)* @nested to i8*), float* %x, float* %xp, i32 %outer, i32 %inner)
48+
ret void
49+
}
50+
51+
; CHECK: define internal void @diffenested
52+
; CHECK: %[[sub:.*]] = add i32 %inner, -1
53+
; CHECK: %{{.*}} = sext i32 %[[sub]] to i64

enzyme/test/Enzyme/ReverseMode/nulluw.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ declare dso_local double @__enzyme_autodiff(i8*, ...)
124124
; CHECK-NEXT: %[[i13:.+]] = getelementptr inbounds i32, i32* %i5_malloccache, i64 %"iv'ac.0"
125125
; CHECK-NEXT: %[[i14:.+]] = load i32, i32* %[[i13]], align 4, !invariant.group ![[ig6]]
126126
; CHECK-NEXT: %[[_unwrap1:.+]] = add i32 %[[i14]], -1
127-
; CHECK-NEXT: %[[_unwrap2:.+]] = zext i32 %[[_unwrap1]] to i64
127+
; CHECK-NEXT: %[[_unwrap2:.+]] = sext i32 %[[_unwrap1]] to i64
128128
; CHECK-NEXT: br label %remat_enter
129129

130130
; CHECK: invertbb7: ; preds = %bb7, %incinvertbb2

enzyme/test/Enzyme/ReverseMode/nulluw_l10.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ declare dso_local double @__enzyme_autodiff(i8*, ...)
124124
; CHECK-NEXT: %[[i13:.+]] = getelementptr inbounds i32, i32* %i5_malloccache, i64 %"iv'ac.0"
125125
; CHECK-NEXT: %[[i14:.+]] = load i32, i32* %[[i13]], align 4, !invariant.group ![[ig6]]
126126
; CHECK-NEXT: %[[_unwrap1:.+]] = add i32 %[[i14]], -1
127-
; CHECK-NEXT: %[[_unwrap2:.+]] = zext i32 %[[_unwrap1]] to i64
127+
; CHECK-NEXT: %[[_unwrap2:.+]] = sext i32 %[[_unwrap1]] to i64
128128
; CHECK-NEXT: br label %remat_enter
129129

130130
; CHECK: invertbb7: ; preds = %bb7, %incinvertbb2

enzyme/test/Enzyme/ReverseMode/scase.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,6 @@ attributes #8 = { noreturn nounwind }
135135

136136
; CHECK: staging: ; preds = %entry
137137
; CHECK-NEXT: %[[_unwrap1:.+]] = add i32 %SINCOSN, -2
138-
; CHECK-NEXT: %[[_unwrap2]] = zext i32 %[[_unwrap1]] to i64
138+
; CHECK-NEXT: %[[_unwrap2]] = sext i32 %[[_unwrap1]] to i64
139139
; CHECK-NEXT: br label %invertfor.body
140140
; CHECK-NEXT: }

0 commit comments

Comments
 (0)