PMU changes: Read PMU PMDEVARCH reg to query cs complaint (#466)

- The SBSA PMU test relies on the CoreSight PMU architecture
  for register memory layout.
- Read the PMDEVARCH register to check the same
  and skip if PMU node not following CS register layout.

Signed-off-by: Sujana M <sujana.murali@arm.com>

Author: Sujana-M

pal/baremetal/sbsa/include/pal_sbsa_common_support.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version  2.0 (the "License");
@@ -35,6 +35,7 @@ typedef struct {
     uint64_t base0;               /* Base address of Page 0 of the PMU*/
     uint64_t base1;               /* Base address of Page 1 of the PMU,
                                    valid only if dual_page_extension is 1*/
+    uint32_t coresight_compliant; /* node coresight compliant or not */
 } PMU_INFO_BLOCK;
 
 typedef struct {
@@ -380,4 +381,4 @@ typedef struct {
 
 void pal_pcc_create_info_table(PCC_INFO_TABLE *PccInfoTable);
 
-#endif
+#endif

pal/baremetal/target/RDN2/sbsa/include/platform_override_sbsa_struct.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -102,6 +102,7 @@ typedef struct {
   uint64_t base0;               /* Base address of Page 0 of the PMU */
   uint64_t base1;               /* Base address of Page 1 of the PMU,
                                      valid only if dual_page_extension is 1 */
+  uint32_t coresight_compliant;  /* node CS arch complaint */
 } PLATFORM_OVERRIDE_PMU_INFO_BLOCK;
 
 typedef struct {

pal/uefi_acpi/sbsa/include/pal_sbsa_uefi.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -38,6 +38,7 @@ typedef struct {
     UINT64 base0;               /* Base address of Page 0 of the PMU*/
     UINT64 base1;               /* Base address of Page 1 of the PMU,
                                    valid only if dual_page_extension is 1*/
+    UINT32 coresight_compliant; /* node is CS arch complaint or not */
 } PMU_INFO_BLOCK;
 
 typedef struct {

val/sbsa/include/sbsa_acs_pmu.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -41,6 +41,7 @@ uint32_t val_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index
                                      uint32_t mon_index, uint32_t eventid);
 uint32_t val_pmu_check_monitor_count_value(uint64_t interface_acpiid, uint32_t count_value,
                                                                           uint32_t eventid);
+void     val_pmu_set_node_coresight_complaint(uint32_t flag, uint32_t node_index);
 
 uint32_t pmu001_entry(uint32_t num_pe);
 uint32_t pmu002_entry(uint32_t num_pe);

val/sbsa/include/sbsa_acs_pmu_reg.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -127,4 +127,7 @@ BITFIELD_DECL(uint32_t, PMSCR_MSI_MPAM_NS, 3, 3)
 BITFIELD_DECL(uint32_t, PMSCR_NAO, 4, 4)
 BITFIELD_DECL(uint32_t, PMSCR_IMPL, 31, 31)
 
+/* PMDEVARCH bit configuration */
+BITFIELD_DECL(uint32_t, PMDEVARCH_ARCHITECT, 31, 21)
+
 #endif /*__PMU_REG_H__ */

val/sbsa/include/sbsa_pal_interface.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -53,6 +53,7 @@ typedef struct {
     uint64_t base0;               /* Base address of Page 0 of the PMU*/
     uint64_t base1;               /* Base address of Page 1 of the PMU,
                                    valid only if dual_page_extension is 1*/
+    uint32_t coresight_compliant; /* node is CS complaint or not */
 } PMU_INFO_BLOCK;
 
 typedef struct {

val/sbsa/include/sbsa_val_interface.h

@@ -161,6 +161,7 @@ typedef enum {
   PMU_NODE_SEC_INST,   /* Secondary instance          */
   PMU_NODE_COUNT,      /* PMU Node count              */
   PMU_NODE_DP_EXTN,    /* Dual page extension support */
+  PMU_NODE_CS_COM,     /* Node is Coresight arch complaint */
 } PMU_INFO_e;
 
 uint32_t val_sbsa_pe_execute_tests(uint32_t level, uint32_t num_pe);

val/sbsa/src/sbsa_acs_pmu.c

@@ -34,6 +34,10 @@ PMU_INFO_TABLE  *g_pmu_info_table;
 void
 val_pmu_create_info_table(uint64_t *pmu_info_table)
 {
+  uint32_t node_index;
+  addr_t base;
+  uint32_t reg_value;
+
   if (pmu_info_table == NULL) {
     val_print(ACS_PRINT_ERR, "\nInput for Create PMU Info table cannot be NULL", 0);
     return;
@@ -46,9 +50,43 @@ val_pmu_create_info_table(uint64_t *pmu_info_table)
   val_print(ACS_PRINT_TEST, " PMU_INFO: Number of PMU units        : %4d\n",
             g_pmu_info_table->pmu_count);
 
+  for (node_index = 0; node_index < g_pmu_info_table->pmu_count; node_index++) {
+      base = val_pmu_get_info(PMU_NODE_BASE0, node_index);
+      reg_value = BITFIELD_READ(PMDEVARCH_ARCHITECT, val_mmio_read(base + REG_PMDEVARCH));
+      /* 0x23B is value for Arm Limited */
+      if (reg_value == 0x23B)
+          val_pmu_set_node_coresight_complaint(0x1, node_index);
+      else {
+          val_pmu_set_node_coresight_complaint(0x0, node_index);
+          val_print(ACS_PRINT_ERR, "\n   PMU node index %d is not CS complaint", node_index);
+      }
+  }
+
   return;
 }
 
+/**
+  @brief  Set if PMU node coresight architecture complaint or not
+**/
+void
+val_pmu_set_node_coresight_complaint(uint32_t flag, uint32_t node_index)
+{
+  PMU_INFO_BLOCK *entry;
+
+  if (g_pmu_info_table == NULL) {
+      val_print(ACS_PRINT_WARN, "\n   APMT info table not found", 0);
+      return;
+  }
+
+  if (node_index > g_pmu_info_table->pmu_count) {
+      val_print(ACS_PRINT_WARN, "\n   Invalid Node index ", 0);
+      return;
+  }
+
+  entry = &g_pmu_info_table->info[node_index];
+  entry->coresight_compliant = flag;
+}
+
 /**
   @brief  Free the memory allocated for the PMU information table
 **/
@@ -100,6 +138,8 @@ val_pmu_get_info(PMU_INFO_e type, uint32_t node_index)
       return g_pmu_info_table->pmu_count;
   case PMU_NODE_DP_EXTN:
       return entry->dual_page_extension;
+  case PMU_NODE_CS_COM:
+      return entry->coresight_compliant;
   default:
         val_print(ACS_PRINT_ERR, "\n   This PMU info option is not supported : %d ", type);
         return 0;